From patchwork Mon Jun 30 23:09:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 442C214003E for ; Tue, 1 Jul 2014 09:21:21 +1000 (EST) Received: from localhost ([::1]:37142 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1ksx-0008If-6i for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:21:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjb-0006vL-Q6 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kjV-0003zp-NU for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:39 -0400 Received: from mail-oa0-f52.google.com ([209.85.219.52]:64247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kjV-0003zb-H3 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:11:33 -0400 Received: by mail-oa0-f52.google.com with SMTP id j17so9714774oag.11 for ; Mon, 30 Jun 2014 16:11:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WCeLyLkC1xgxm6+oOkIu5PFfwXgJs9iCTsBTvekRubs=; b=DqtMIeZ2GT+WdNj3p9UlZg7RwGCNHjFAM2sn6S5/xgQ1q2DSRoPFXDOmeqWd6O/T6r eD/4jEhLnI/k+GLdR+MM7zTxGIRbEfTh91Qie6zyHfcdpDWIMkQcbSO3yij6yvk3NJU+ k58PA5IyMm/+G1gUIcAn14Cd2CagJxWzxUtNr2yAXEdYfZj4Xj2Op+te4wkkTSXVuUvk 5nyUDijfKrXjbtrH26ra/OkQofUg86ET/e780U0QmP48TciFhAqV1Bg9KrCC4VqRDjBy LBttUy+b0LS1jToxSHWgDYUogHpNDuSEWHRRdDY648LXLZxKFwrfj41bzY3qfTFBuUvm D3Ag== X-Gm-Message-State: ALoCoQnksFe0WytGTPih+A9tOy8lhJ51Y5APRl0Z5FGhLvfpJtsuBaIc7U5uheNOFD3eLXOBXi/m X-Received: by 10.60.45.130 with SMTP id n2mr45484615oem.12.1404169893157; Mon, 30 Jun 2014 16:11:33 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.11.31 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:11:32 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:33 -0500 Message-Id: <1404169773-20264-34-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.219.52 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Greg Bellows This patch adds code to mark duplicate CP register registrations as NO_MIGRATE to avoid duplicate migrations. Signed-off-by: Greg Bellows --- target-arm/helper.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3bc55fe..7c1e2eb 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2339,7 +2339,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, - { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, + /* SCR will always be registered for v7, but not necessarily for v8, so + * this entry is marked to allow migration to be handled by the v7 + * registration instance. + */ + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .writefn = scr_write }, @@ -2958,6 +2962,11 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, * banked registers but later only fieldoffset is used. */ r2->fieldoffset = r->bank_fieldoffsets[nsbit]; + } else if (!nsbit) { + /* The register is not banked so we only want to allow migration of + * the non-secure instance. + */ + r2->type |= ARM_CP_NO_MIGRATE; } if (r->state == ARM_CP_STATE_BOTH) {