From patchwork Mon Jun 30 23:09:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 365811 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 04E151400B5 for ; Tue, 1 Jul 2014 09:17:18 +1000 (EST) Received: from localhost ([::1]:37102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kp2-0003fg-5E for incoming@patchwork.ozlabs.org; Mon, 30 Jun 2014 19:17:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kiq-0005iQ-9U for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X1kil-0003I2-19 for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:52 -0400 Received: from mail-ob0-f182.google.com ([209.85.214.182]:47004) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X1kik-0003HX-FY for qemu-devel@nongnu.org; Mon, 30 Jun 2014 19:10:46 -0400 Received: by mail-ob0-f182.google.com with SMTP id nu7so9609747obb.13 for ; Mon, 30 Jun 2014 16:10:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c7ObWyJGEfiAdt12pMoBzT6QU6rC56ycJtnYigk/K/U=; b=KpjfsHzMcloT9aYxGcFecR+UulmRy0NX7hsktNx3vVIwl04IzB2cC9ABgY+0uewgX6 NmerGGC/ImXmWd6QLIRMvwsN3JDGW6PVH+Ujq7Wm01XE56BDUyWMQeF0Y8fKpvwWQD8Q VUdI9nlKPFYGsgLl0lQi0eN3gdznhlzBUGM1KMK0qsZR7rYTNWBxW6maquJGkzkUi4Uk nobUGU+GgdMQGbtSzMpKJBz/9i4U/SNgPbUnjCBS0W9pIbRHZhfaie55fqwo3a4RkEWh QEc8zUHzh1Cr+ru/dYyUBQ/SKrwd+R/kHmRVK3KpqIXwzJ8JJnx3p5581bwCn9d/I8tj zRYw== X-Gm-Message-State: ALoCoQmCiFuXIUGlbw/ekL855SA7iHU9/8EXHbBnzZX8wHwYE0xAmPVY8ydZbamQq9mggrpTm2aM X-Received: by 10.60.115.67 with SMTP id jm3mr45530078oeb.8.1404169845987; Mon, 30 Jun 2014 16:10:45 -0700 (PDT) Received: from gbellows-linaro.bellowshome.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id cu7sm76370192oec.12.2014.06.30.16.10.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 30 Jun 2014 16:10:44 -0700 (PDT) From: greg.bellows@linaro.org To: qemu-devel@nongnu.org Date: Mon, 30 Jun 2014 18:09:11 -0500 Message-Id: <1404169773-20264-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> References: <1404169773-20264-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.182 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Fabian Aggeler , Greg Bellows , serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v4 11/33] target-arm: add async excp target_el&mode function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Adds a dedicated function for IRQ and FIQ exceptions to determine target_el and mode (Aarch32) according to tables in ARM ARMv8 and ARM ARM v7. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows -------------- v3 -> v4 - Fixed arm_phys_excp_target_el() 0/0/0 case to return excp_mode when EL<2 rather than ABORT. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 3 ++ target-arm/helper.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 140 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7b2817c..1e8d5ee 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -784,6 +784,9 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); +inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode, + uint32_t excp_idx, uint32_t cur_el, + bool secure); /* Interface between CPU and Interrupt controller. */ void armv7m_nvic_set_pending(void *opaque, int irq); diff --git a/target-arm/helper.c b/target-arm/helper.c index 2e285ab..4233ae3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3239,6 +3239,21 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) return 0; } +inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode, + uint32_t excp_idx, uint32_t cur_el, + bool secure) +{ + switch (excp_idx) { + case EXCP_IRQ: + *target_mode = ARM_CPU_MODE_IRQ; + break; + case EXCP_FIQ: + *target_mode = ARM_CPU_MODE_FIQ; + break; + } + return 1; +} + unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) { return 1; @@ -3300,6 +3315,128 @@ void switch_mode(CPUARMState *env, int mode) } /* + * Determine the target EL for physical exceptions + */ +inline uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t *target_mode, + uint32_t excp_idx, uint32_t cur_el, + bool secure) +{ + CPUARMState *env = cs->env_ptr; + uint32_t target_el = 1; + uint32_t excp_mode = 0; + + bool scr_routing = 0; /* IRQ, FIQ, EA */ + bool hcr_routing = 0; /* IMO, FMO, AMO */ + + switch (excp_idx) { + case EXCP_IRQ: + scr_routing = (env->cp15.scr_el3 & SCR_IRQ); + hcr_routing = (env->cp15.hcr_el2 & HCR_IMO); + excp_mode = ARM_CPU_MODE_IRQ; + break; + case EXCP_FIQ: + scr_routing = (env->cp15.scr_el3 & SCR_FIQ); + hcr_routing = (env->cp15.hcr_el2 & HCR_FMO); + excp_mode = ARM_CPU_MODE_FIQ; + } + + /* If HCR.TGE is set all exceptions that would be routed to EL1 are + * routed to EL2 (in non-secure world). + */ + if (arm_feature(env, ARM_FEATURE_EL2) && (env->cp15.hcr_el2 & HCR_TGE)) { + hcr_routing = 1; + } + + /* Determine target EL according to ARM ARMv8 tables G1-15 and G1-16 */ + if (arm_el_is_aa64(env, 3)) { + /* EL3 in Aarch64 */ + if (scr_routing) { + /* IRQ|FIQ|EA == 1 */ + target_el = 3; + } else { + if (hcr_routing) { + /* IRQ|FIQ|EA == 0 + * IMO|FMO|AMO == 1 */ + if (secure) { + /* Secure */ + target_el = 1; + if (!arm_el_is_aa64(env, 1)) { + /* EL1 using Aarch32 */ + *target_mode = ARM_CPU_MODE_ABT; + } + } else if (cur_el < 2) { + /* Non-Secure goes to EL2 */ + target_el = 2; + if (!arm_el_is_aa64(env, 2)) { + /* EL2 using Aarch32 */ + *target_mode = ARM_CPU_MODE_HYP; + } + } + } else if (env->cp15.scr_el3 & SCR_RW) { + /* IRQ|FIQ|EA == 0 + * IMO|FMO|AMO == 0 + * RW == 1 (Next lower level is Aarch64) + */ + if (cur_el < 2) { + target_el = 1; + } else { + /* Interrupt not taken but remains pending */ + } + } else { + /* IRQ|FIQ|EA == 0 + * IMO|FMO|AMO == 0 + * RW == 0 (Next lower level is Aarch64) + */ + if (cur_el < 2) { + target_el = 1; + *target_mode = excp_mode; + } else if (cur_el == 2) { + target_el = 2; + *target_mode = ARM_CPU_MODE_HYP; + } else { + /* Interrupt not taken but remains pending */ + } + } + } + } else { + /* EL3 in Aarch32 */ + if (scr_routing) { + /* IRQ|FIQ|EA == 1 */ + target_el = 3; + *target_mode = ARM_CPU_MODE_MON; + } else { + if (hcr_routing) { + /* IRQ|FIQ|EA == 0 + * IMO|FMO|AMO == 1 + */ + if (secure) { + target_el = 3; + *target_mode = excp_mode; + } else { + target_el = 2; + *target_mode = ARM_CPU_MODE_HYP; + } + } else { + /* IRQ|FIQ|EA == 0 + * IMO|FMO|AMO == 0 + */ + if (cur_el < 2) { + target_el = 1; + *target_mode = excp_mode; + } else if (cur_el == 2) { + target_el = 2; + *target_mode = ARM_CPU_MODE_HYP; + } else if (secure) { + target_el = 3; + *target_mode = excp_mode; + } + } + } + } + return target_el; +} + +/* * Determine the target EL for a given exception type. */ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)