From patchwork Fri Jun 20 12:11:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 362190 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D2436140084 for ; Fri, 20 Jun 2014 22:12:19 +1000 (EST) Received: from localhost ([::1]:40446 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wxxg0-0000fA-TV for incoming@patchwork.ozlabs.org; Fri, 20 Jun 2014 08:12:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40187) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxxfP-0007w4-CW for qemu-devel@nongnu.org; Fri, 20 Jun 2014 08:11:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WxxfI-0001xf-RA for qemu-devel@nongnu.org; Fri, 20 Jun 2014 08:11:39 -0400 Received: from mail-wg0-x22c.google.com ([2a00:1450:400c:c00::22c]:51384) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WxxfI-0001xN-Kw for qemu-devel@nongnu.org; Fri, 20 Jun 2014 08:11:32 -0400 Received: by mail-wg0-f44.google.com with SMTP id x13so3628138wgg.27 for ; Fri, 20 Jun 2014 05:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=wbt9Q7IycGMBCDEp8XT/csBeu+mv1rO39C9P1KzCKEE=; b=XKcr0lRT0RKsntFHCIVVNnuNWFy3cpvir7Elftn0fISjzp0IEO1+UPCn6ejfTBvkiM MryCB3ouwcnCfozezi3W7qZ7z9btLmtdZgbxm1Z8/wXCIBUK3fMKovSOzfWu/q4x+aBx cCw9rm+MiPoDTQSf6RwhjTAEwsIJ8n7BG7rP2uD417OFHxzp9FT5W4xL7kQgApjRyldw h6H/kmagb7McRyP9VB2jxvcCPMoaRvAZddf+DOWdFJwivnXMQIotj9r/1Q3Lu22DRM44 mjYZys9GUOSDI4qQum0i7w2NPSj48i8P94umYtEwktyI65NnJ53KgynAxax9uFP0b/Mn id4g== X-Received: by 10.194.91.144 with SMTP id ce16mr3878286wjb.18.1403266291892; Fri, 20 Jun 2014 05:11:31 -0700 (PDT) Received: from playground.station (net-37-117-140-88.cust.vodafonedsl.it. [37.117.140.88]) by mx.google.com with ESMTPSA id dj2sm4222458wib.11.2014.06.20.05.11.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jun 2014 05:11:31 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 20 Jun 2014 14:11:11 +0200 Message-Id: <1403266283-1517-3-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1403266283-1517-1-git-send-email-pbonzini@redhat.com> References: <1403266283-1517-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:400c:c00::22c Cc: James Hogan , Aurelien Jarno Subject: [Qemu-devel] [PULL 02/14] target-mips: Reset CPU timer consistently X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: James Hogan The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is reset at machine initialisation, including starting the timeout. Both registers however are placed before mvp in CPUMIPSState so they will both be zeroed on reset by the memset in mips_cpu_reset() including soon after init. This doesn't take into account that the timer may be running, in which case env->CP0_Count will represent the delta against the VM clock and the timeout will need updating. At init time (cpu_mips_clock_init()), lets only create the timer. Setting Count = 1 and starting the timer (cpu_mips_store_count()) can be done at reset time from cpu_state_reset(), which is after the memset. There is also no need to set CP0_Compare = 0 as that is already handled by the memset. Note that a reset occurs from mips_cpu_realizefn() which is before the machine init callback has had a chance to set up the CPU interrupts and the CPU timer, so env->timer will be NULL. This case is handled explicitly in cpu_mips_store_count(), treating the timer as disabled (which will also be the right thing to do when KVM support is added). Reported-by: Paolo Bonzini Signed-off-by: James Hogan Cc: Aurelien Jarno Signed-off-by: Paolo Bonzini --- hw/mips/cputimer.c | 9 ++++++--- target-mips/translate.c | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c index c8b4b00..6900a74 100644 --- a/hw/mips/cputimer.c +++ b/hw/mips/cputimer.c @@ -85,7 +85,12 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env) void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) + /* + * This gets called from cpu_state_reset(), potentially before timer init. + * So env->timer may be NULL, which is also the case with KVM enabled so + * treat timer as disabled in that case. + */ + if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) env->CP0_Count = count; else { /* Store new count register */ @@ -142,6 +147,4 @@ static void mips_timer_cb (void *opaque) void cpu_mips_clock_init (CPUMIPSState *env) { env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env); - env->CP0_Compare = 0; - cpu_mips_store_count(env, 1); } diff --git a/target-mips/translate.c b/target-mips/translate.c index 76deb7b..d95ab9e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -16043,6 +16043,8 @@ void cpu_state_reset(CPUMIPSState *env) /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + cpu_mips_store_count(env, 1); + if (env->CP0_Config3 & (1 << CP0C3_MT)) { int i;