From patchwork Wed Jun 11 15:19:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 358747 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E3275140085 for ; Thu, 12 Jun 2014 01:24:55 +1000 (EST) Received: from localhost ([::1]:47258 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WukOT-0007Fh-JT for incoming@patchwork.ozlabs.org; Wed, 11 Jun 2014 11:24:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55235) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WukKf-0001Ct-QX for qemu-devel@nongnu.org; Wed, 11 Jun 2014 11:21:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WukKb-00042B-5w for qemu-devel@nongnu.org; Wed, 11 Jun 2014 11:20:57 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:53590) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WukKb-000421-0T for qemu-devel@nongnu.org; Wed, 11 Jun 2014 11:20:53 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 7C0B5494C6186; Wed, 11 Jun 2014 16:20:48 +0100 (IST) Received: from localhost.localdomain (192.168.14.85) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Wed, 11 Jun 2014 16:20:50 +0100 From: Leon Alrae To: Date: Wed, 11 Jun 2014 16:19:33 +0100 Message-ID: <1402499992-64851-4-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> References: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net Subject: [Qemu-devel] [PATCH v2 03/22] target-mips: add SELEQZ and SELNEZ instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Leon Alrae Reviewed-by: Aurelien Jarno --- v2: * correct conditions to match instruction name --- disas/mips.c | 8 ++++++++ target-mips/translate.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+), 0 deletions(-) diff --git a/disas/mips.c b/disas/mips.c index 2106b57..b950e53 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -521,6 +521,8 @@ struct mips_opcode #define INSN_ISA64 0x00000040 #define INSN_ISA32R2 0x00000080 #define INSN_ISA64R2 0x00000100 +#define INSN_ISA32R6 0x00000200 +#define INSN_ISA64R6 0x00000400 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x0000f000 @@ -585,6 +587,8 @@ struct mips_opcode #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) +#define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6) +#define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6) /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -1121,6 +1125,8 @@ extern const int bfd_mips16_num_opcodes; #define I64 INSN_ISA64 #define I33 INSN_ISA32R2 #define I65 INSN_ISA64R2 +#define I32R6 INSN_ISA32R6 +#define I64R6 INSN_ISA64R6 /* MIPS64 MIPS-3D ASE support. */ #define I16 INSN_MIPS16 @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] = them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, membership */ +{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, +{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 }, {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 }, {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */ diff --git a/target-mips/translate.c b/target-mips/translate.c index dbb3746..4eb8a61 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -189,6 +189,9 @@ enum { OPC_MOVZ = 0x0A | OPC_SPECIAL, OPC_MOVN = 0x0B | OPC_SPECIAL, + OPC_SELEQZ = 0x35 | OPC_SPECIAL, + OPC_SELNEZ = 0x37 | OPC_SPECIAL, + OPC_MOVCI = 0x01 | OPC_SPECIAL, /* Special */ @@ -2406,6 +2409,14 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc, tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); opn = "movz"; break; + case OPC_SELNEZ: + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1); + opn = "selnez"; + break; + case OPC_SELEQZ: + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); + opn = "seleqz"; + break; } tcg_temp_free(t2); tcg_temp_free(t1); @@ -14480,6 +14491,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx) INSN_LOONGSON2E | INSN_LOONGSON2F); gen_cond_move(ctx, op1, rd, rs, rt); break; + case OPC_SELEQZ: + case OPC_SELNEZ: + check_insn(ctx, ISA_MIPS32R6); + gen_cond_move(ctx, op1, rd, rs, rt); + break; case OPC_ADD ... OPC_SUBU: gen_arith(ctx, op1, rd, rs, rt); break;