From patchwork Tue Jun 10 23:55:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabian Aggeler X-Patchwork-Id: 358448 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4A6EC14007F for ; Wed, 11 Jun 2014 10:10:52 +1000 (EST) Received: from localhost ([::1]:42668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuW7t-0007uO-Uk for incoming@patchwork.ozlabs.org; Tue, 10 Jun 2014 20:10:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtQ-0007vW-Nv for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVtG-0004J3-Si for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:52 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:2337) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtG-0004IY-Jg for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:42 -0400 Received: from CAS20.d.ethz.ch (172.31.51.110) by edge20.ethz.ch (82.130.99.26) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 11 Jun 2014 01:55:36 +0200 Received: from qemubox.ethz.ch (129.132.211.172) by CAS20.d.ethz.ch (172.31.51.110) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 11 Jun 2014 01:55:41 +0200 From: Fabian Aggeler To: Date: Wed, 11 Jun 2014 01:55:11 +0200 Message-ID: <1402444514-19658-30-git-send-email-aggelerf@ethz.ch> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 X-Originating-IP: [129.132.211.172] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 82.130.99.26 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v3 29/32] target-arm: make IFAR/DFAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Conflicts: target-arm/helper.c --- target-arm/cpu.c | 2 +- target-arm/cpu.h | 21 ++++++++++++++++++++- target-arm/helper-a64.c | 14 ++++++++++++-- target-arm/helper.c | 25 ++++++++++++++----------- 4 files changed, 47 insertions(+), 15 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f469715..6be35ed 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -463,7 +463,7 @@ static void arm1026_initfn(Object *obj) ARMCPRegInfo ifar = { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), + .fieldoffset = offsetofhigh32(CPUARMState, cp15.ifar_ns), .resetvalue = 0 }; define_one_arm_cp_reg(cpu, &ifar); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 71782cf..7f5124c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -279,7 +279,26 @@ typedef struct CPUARMState { }; }; uint32_t c6_region[8]; /* MPU base/size registers. */ - uint64_t far_el[4]; /* Fault address registers. */ + union { /* Fault address registers. */ + struct { +#ifdef HOST_WORDS_BIGENDIAN + uint32_t ifar_ns; + uint32_t dfar_ns; + uint32_t ifar_s; + uint32_t dfar_s; +#else + uint32_t dfar_ns; + uint32_t ifar_ns; + uint32_t dfar_s; + uint32_t ifar_s; +#endif + }; + struct { + uint64_t far_el1; + uint64_t far_el2; + }; + }; + uint64_t far_el3; uint64_t par_el1; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index dbbf012..1fc0d3c 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -481,9 +481,19 @@ void aarch64_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - env->cp15.far_el[new_el] = env->exception.vaddress; + switch (new_el) { + case 3: + env->cp15.far_el3 = env->exception.vaddress; + break; + case 2: + env->cp15.far_el2 = env->exception.vaddress; + break; + case 1: + env->cp15.far_el1 = env->exception.vaddress; + break; + } qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el[new_el]); + env->exception.vaddress); case EXCP_BKPT: case EXCP_UDEF: case EXCP_SWI: diff --git a/target-arm/helper.c b/target-arm/helper.c index 793985e..47bf7a7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -536,7 +536,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { .access = PL0_W, .type = ARM_CP_NOP }, { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), + offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue = 0, }, /* Watchpoint Fault Address Register : should actually only be present * for 1136, 1176, 11MPCore. @@ -1523,11 +1524,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write, .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s), offsetoflow32(CPUARMState, cp15.ttbcr_ns) } }, - /* 64-bit FAR; this entry also gives us the AArch32 DFAR */ - { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH, + { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), + offsetof(CPUARMState, cp15.dfar_ns) } }, + { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), - .resetvalue = 0, }, + .access = PL1_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.far_el1), + }, REGINFO_SENTINEL }; @@ -2191,7 +2196,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el2) }, { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, - .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el2) }, { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, @@ -2303,7 +2308,7 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el3) }, { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, - .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el3) }, { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, @@ -3838,8 +3843,7 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); - env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, - env->exception.vaddress); + A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; @@ -3849,8 +3853,7 @@ void arm_cpu_do_interrupt(CPUState *cs) break; case EXCP_DATA_ABORT: A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); - env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, - env->exception.vaddress); + A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", env->exception.fsr, (uint32_t)env->exception.vaddress);