From patchwork Tue Jun 10 23:55:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabian Aggeler X-Patchwork-Id: 358446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 268B8140096 for ; Wed, 11 Jun 2014 10:06:19 +1000 (EST) Received: from localhost ([::1]:42626 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuW3U-0003e8-ML for incoming@patchwork.ozlabs.org; Tue, 10 Jun 2014 20:06:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtO-0007s2-V5 for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVtG-0004Ic-BZ for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:50 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:14849) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtG-0004IJ-1r for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:42 -0400 Received: from CAS20.d.ethz.ch (172.31.51.110) by edge10.ethz.ch (82.130.75.186) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 11 Jun 2014 01:55:38 +0200 Received: from qemubox.ethz.ch (129.132.211.172) by CAS20.d.ethz.ch (172.31.51.110) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 11 Jun 2014 01:55:40 +0200 From: Fabian Aggeler To: Date: Wed, 11 Jun 2014 01:55:10 +0200 Message-ID: <1402444514-19658-29-git-send-email-aggelerf@ethz.ch> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 X-Originating-IP: [129.132.211.172] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 82.130.75.186 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v3 28/32] target-arm: make DFSR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 13 ++++++++++++- target-arm/helper-a64.c | 17 ++++++++++++++--- target-arm/helper.c | 15 ++++++++------- 3 files changed, 34 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 54c51a4..71782cf 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -266,7 +266,18 @@ typedef struct CPUARMState { uint32_t ifsr32_el2; }; }; - uint64_t esr_el[4]; + union { + struct { + uint64_t dfsr_ns; + uint64_t hsr; + uint64_t dfsr_s; + }; + struct { + uint64_t esr_el1; + uint64_t esr_el2; + uint64_t esr_el3; + }; + }; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index d7522b6..dbbf012 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -447,6 +447,18 @@ void aarch64_cpu_do_interrupt(CPUState *cs) target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); int i; + uint64_t *target_esr; + switch (new_el) { + case 3: + target_esr = &env->cp15.esr_el3; + break; + case 2: + target_esr = &env->cp15.esr_el2; + break; + case 1: + target_esr = &env->cp15.esr_el1; + break; + } if (arm_current_pl(env) < new_el) { if (env->aarch64) { @@ -477,8 +489,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) case EXCP_SWI: case EXCP_HVC: case EXCP_SMC: - env->cp15.esr_el[new_el] = env->exception.syndrome; - break; + *target_esr = env->exception.syndrome; case EXCP_IRQ: case EXCP_VIRQ: addr += 0x80; @@ -498,7 +509,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } else { env->banked_spsr[0] = cpsr_read(env); if (!env->thumb) { - env->cp15.esr_el[new_el] |= 1 << 25; + *target_esr |= 1 << 25; } env->elr_el[new_el] = env->regs[15]; diff --git a/target-arm/helper.c b/target-arm/helper.c index f51498a..793985e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1492,7 +1492,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), + offsetoflow32(CPUARMState, cp15.dfsr_ns) }, .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .resetvalue = 0, @@ -1501,7 +1502,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, + .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = 0, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, @@ -1565,7 +1566,7 @@ static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo omap_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1), .resetvalue = 0, }, { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, @@ -2187,7 +2188,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, - .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el2) }, { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, @@ -2299,7 +2300,7 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, - .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el3) }, { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, @@ -3847,11 +3848,11 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; case EXCP_DATA_ABORT: - env->cp15.esr_el[1] = env->exception.fsr; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - (uint32_t)env->cp15.esr_el[1], + env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x10;