diff mbox

[RCF,8/8] target-arm: remove final users of pstate_write

Message ID 1401726122-11132-9-git-send-email-alex.bennee@linaro.org
State New
Headers show

Commit Message

Alex Bennée June 2, 2014, 4:22 p.m. UTC 
This converts all users of pstate_write to use the common state
save/restore functionality.

Comments

Alex Bennée June 3, 2014, 10:19 a.m. UTC | #1 
Alex Bennée writes:

> This converts all users of pstate_write to use the common state
> save/restore functionality.

Oops, now I'll clean that up. I need to decide if it worth merge the
xpsr_ stuff anyway?

There is also some commented out code in the main save_state_to_spsr()
function which I need to clean out.
diff mbox

Patch

diff --git a/linux-user/signal.c b/linux-user/signal.c
index c155bbc..48885e2 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1290,7 +1290,7 @@  static int target_restore_sigframe(CPUARMState *env,
     __get_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
     __get_user(env->pc, &sf->uc.tuc_mcontext.pc);
     __get_user(pstate, &sf->uc.tuc_mcontext.pstate);
-    pstate_write(env, pstate);
+    restore_state_from_spsr(env, pstate);
 
     __get_user(magic, &aux->fpsimd.head.magic);
     __get_user(size, &aux->fpsimd.head.size);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c4727f7..e6723dc 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -460,20 +460,6 @@  int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 #define PSTATE_MODE_EL1t 4
 #define PSTATE_MODE_EL0t 0
 
-/* Update the current PSTATE value. This doesn't include nRW which
- * indicates if we are in 64 or 32 bit mode */
-static inline void pstate_write(CPUARMState *env, uint32_t val)
-{
-    g_assert(is_a64(env));
-
-    env->ZF = (~val) & PSTATE_Z;
-    env->NF = val;
-    env->CF = (val >> 29) & 1;
-    env->VF = (val << 3) & 0x80000000;
-    env->daif = val & PSTATE_DAIF;
-    env->pstate = val & ~AARCH64_CACHED_PSTATE_BITS;
-}
-
 /* ARMv7-M ARM B1.4.2, special purpose program status register xPSR */
 static inline uint32_t xpsr_read(CPUARMState *env)
 {
diff --git a/target-arm/gdbstub64.c b/target-arm/gdbstub64.c
index 76d1b91..366335a 100644
--- a/target-arm/gdbstub64.c
+++ b/target-arm/gdbstub64.c
@@ -63,7 +63,7 @@  int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         return 8;
     case 33:
         /* SPSR */
-        pstate_write(env, tmp);
+        restore_state_from_spsr(env, tmp);
         return 4;
     }
     /* Unknown register.  */
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 1ca3164..bb48014 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -507,9 +507,8 @@  void aarch64_cpu_do_interrupt(CPUState *cs)
         env->condexec_bits = 0;
     }
 
-    // TODO: restore_state_from_spsr()
-    env->aarch64 = 1;
-    pstate_write(env, PSTATE_DAIF | PSTATE_MODE_EL1h);
+    /* start IRQ with a clean program state */
+    restore_state_from_spsr(env, PSTATE_DAIF | PSTATE_MODE_EL1h);
 
     env->pc = addr;
     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index 83df952..8578fa9 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -222,7 +222,7 @@  int kvm_arch_get_registers(CPUState *cs)
     if (ret) {
         return ret;
     }
-    pstate_write(env, val);
+    restore_state_from_spsr(env, val);
 
     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
      * QEMU side we keep the current SP in xregs[31] as well.