From patchwork Fri May 30 17:18:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabian Aggeler X-Patchwork-Id: 354282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BF6521400D8 for ; Sat, 31 May 2014 03:19:27 +1000 (EST) Received: from localhost ([::1]:55685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqQSi-0006tm-QB for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 13:19:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqQSN-0006cH-EW for qemu-devel@nongnu.org; Fri, 30 May 2014 13:19:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqQSG-0004b0-MN for qemu-devel@nongnu.org; Fri, 30 May 2014 13:19:03 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:47982) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqQSG-0004aJ-DN for qemu-devel@nongnu.org; Fri, 30 May 2014 13:18:56 -0400 Received: from CAS21.d.ethz.ch (172.31.51.111) by edge10.ethz.ch (82.130.75.186) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 30 May 2014 19:18:50 +0200 Received: from qemubox.inf.ethz.ch (192.33.93.3) by CAS21.d.ethz.ch (172.31.51.111) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 30 May 2014 19:18:54 +0200 From: Fabian Aggeler To: Date: Fri, 30 May 2014 19:18:47 +0200 Message-ID: <1401470327-23417-1-git-send-email-aggelerf@ethz.ch> X-Mailer: git-send-email 1.8.3.2 MIME-Version: 1.0 X-Originating-IP: [192.33.93.3] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 82.130.75.186 Cc: peter.maydell@linaro.org, serge.fdrv@gmail.com, greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH] target-arm: set SBOP/SBZP bits of SCTLR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ARM ARM v7 specifies SBOP/SBZP bits for v5/v6/v7. This patch sets these bits on every sctlr_write(). In ARMv8 most of them are RES0/RES1. Signed-off-by: Fabian Aggeler --- Previously part of TZ patchset but now includes handling for SBOP/SBZP bits in ARMv5/v6/v7. Not sure whether using the SCTLR_* macros makes it less readable than without them. target-arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 10b965e..443337a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2234,6 +2234,43 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } + if (arm_feature(env, ARM_FEATURE_V8)) { + /* Lots of bits are now RES0/RES1 */ + } else if (arm_feature(env, ARM_FEATURE_V7)) { + /* In ARMv7 set bits to zero/one as follows + * RAO/SBOP: [23:22], [18], [16], [6], [4:3] + * UNK/SBZP or RAZ/SBZP: [31], [26], [15], [9:7] + */ + value |= SCTLR_XP | SCTLR_U | + SCTLR_nTWE | SCTLR_nTWI | SCTLR_L | + SCTLR_P | SCTLR_W; + value &= ~((1U << 31) | SCTLR_L2 | SCTLR_L4 | + SCTLR_R | SCTLR_S | SCTLR_B); + } else if (arm_feature(env, ARM_FEATURE_V6K)) { + /* In ARMv6K set bits to zero/one as follows + * RAO/SBOP: [18], [16], [6:4] + * UNK/SBZP or RAZ/SBZP: [31], [20:19], [10] + */ + value |= SCTLR_IT | SCTLR_DT | + SCTLR_L | SCTLR_D | SCTLR_P; + value &= ~((1U << 31) | SCTLR_WXN | SCTLR_F); + } else if (arm_feature(env, ARM_FEATURE_V6)) { + /* In ARMv6 set bits to zero/one as follows + * RAO/SBOP: [18], [16], [6:4] + * UNK/SBZP or RAZ/SBZP: [31], [29:28], [20:19], [17], [10] + */ + value |= SCTLR_IT | SCTLR_DT | + SCTLR_L | SCTLR_D | SCTLR_P; + value &= ~((1U << 31) | + SCTLR_AFE | SCTLR_TRE | + SCTLR_ST | SCTLR_WXN | + SCTLR_HA | + SCTLR_F); + } else { + /* Bits [31:16] are UNK/SBZP in ARMv4/ARMv5 */ + value &= 0x0000ffff; + } + env->cp15.c1_sys = value; /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */