diff mbox

[21/21] target-mips: use pointers referring to appropriate decoding function

Message ID 1401461279-59617-22-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae May 30, 2014, 2:47 p.m. UTC 
After selecting CPU in QEMU the base ISA will not change. Therefore
introducing *_arch function pointers that are set in cpu_state_reset to
point at the appropriate SPECIAL and SPECIAL3 decoding functions, and avoid
unnecessary 'if' statements.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c |   32 +++++++++++++++++++++-----------
 1 files changed, 21 insertions(+), 11 deletions(-)
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 08182a6..3889988 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15685,6 +15685,13 @@  static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
 
 /* End MIPSDSP functions. */
 
+/* Some instructions from MIPS32R6 and pre-MIPS32R6 have identical encoding.
+
+   decode_opc_*_arch are pointing at the appropriate decoding functions
+   depending on a base ISA supported by selected MIPS CPU. */
+static void (*decode_opc_special_arch) (CPUMIPSState*, DisasContext*);
+static void (*decode_opc_special3_arch) (CPUMIPSState*, DisasContext*);
+
 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd, sa;
@@ -16049,11 +16056,8 @@  static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
         break;
 #endif
     default:
-        if (ctx->insn_flags & ISA_MIPS32R6) {
-            decode_opc_special_r6(env, ctx);
-        } else {
-            decode_opc_special_legacy(env, ctx);
-        }
+        decode_opc_special_arch(env, ctx);
+        break;
     }
 }
 
@@ -16825,12 +16829,9 @@  static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
             tcg_temp_free(t0);
         }
         break;
-    default:            /* Invalid */
-        if (ctx->insn_flags & ISA_MIPS32R6) {
-            decode_opc_special3_r6(env, ctx);
-        } else {
-            decode_opc_special3_legacy(env, ctx);
-        }
+    default:
+        decode_opc_special3_arch(env, ctx);
+        break;
     }
 }
 
@@ -17862,6 +17863,15 @@  void cpu_state_reset(CPUMIPSState *env)
     env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
     env->insn_flags = env->cpu_model->insn_flags;
 
+    /* Select decoding functions appropriate for supported ISA */
+    if (env->insn_flags & ISA_MIPS32R6) {
+        decode_opc_special_arch = decode_opc_special_r6;
+        decode_opc_special3_arch = decode_opc_special3_r6;
+    } else {
+        decode_opc_special_arch = decode_opc_special_legacy;
+        decode_opc_special3_arch = decode_opc_special3_legacy;
+    }
+
 #if defined(CONFIG_USER_ONLY)
     env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
 # ifdef TARGET_MIPS64