From patchwork Fri May 30 13:55:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 354230 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 94FFD1400D6 for ; Sat, 31 May 2014 01:34:54 +1000 (EST) Received: from localhost ([::1]:54606 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqO0P-0003Cz-F6 for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 10:42:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55809) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqNy3-0007Kr-4D for qemu-devel@nongnu.org; Fri, 30 May 2014 10:39:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqNy1-0006yE-S0 for qemu-devel@nongnu.org; Fri, 30 May 2014 10:39:35 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:48327) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqNy1-0006s8-L9 for qemu-devel@nongnu.org; Fri, 30 May 2014 10:39:33 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WqNHJ-0007IH-GK; Fri, 30 May 2014 14:55:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 30 May 2014 14:55:25 +0100 Message-Id: <1401458125-27977-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1401458125-27977-1-git-send-email-peter.maydell@linaro.org> References: <1401458125-27977-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Ard Biesheuvel , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Subject: [Qemu-devel] [PATCH 9/9] target-arm: A64: Implement two-register SHA instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the two-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell --- linux-user/elfload.c | 2 ++ target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 396a808..68b9793 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -541,6 +541,8 @@ static uint32_t get_elf_hwcap(void) do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0) GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_AES); GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL); + GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); + GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); #undef GET_FEATURE diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 1b475cd..e5d9b7b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -84,6 +84,7 @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); +typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); /* initialize TCG globals. */ @@ -10676,7 +10677,49 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) */ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int size = extract32(insn, 22, 2); + int opcode = extract32(insn, 12, 5); + int rn = extract32(insn, 5, 5); + int rd = extract32(insn, 0, 5); + CryptoTwoOpEnvFn *genfn; + int feature; + TCGv_i32 tcg_rd_regno, tcg_rn_regno; + + if (size != 0) { + unallocated_encoding(s); + return; + } + + switch (opcode) { + case 0: /* SHA1H */ + feature = ARM_FEATURE_V8_SHA1; + genfn = gen_helper_crypto_sha1h; + break; + case 1: /* SHA1SU1 */ + feature = ARM_FEATURE_V8_SHA1; + genfn = gen_helper_crypto_sha1su1; + break; + case 2: /* SHA256SU0 */ + feature = ARM_FEATURE_V8_SHA256; + genfn = gen_helper_crypto_sha256su0; + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, feature)) { + unallocated_encoding(s); + return; + } + + tcg_rd_regno = tcg_const_i32(rd << 1); + tcg_rn_regno = tcg_const_i32(rn << 1); + + genfn(cpu_env, tcg_rd_regno, tcg_rn_regno); + + tcg_temp_free_i32(tcg_rd_regno); + tcg_temp_free_i32(tcg_rn_regno); } /* C3.6 Data processing - SIMD, inc Crypto