From patchwork Fri May 30 07:28:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 353907 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 36F62140092 for ; Fri, 30 May 2014 17:34:36 +1000 (EST) Received: from localhost ([::1]:51897 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHKk-00013J-4k for incoming@patchwork.ozlabs.org; Fri, 30 May 2014 03:34:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49019) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHKE-00009Q-Sb for qemu-devel@nongnu.org; Fri, 30 May 2014 03:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WqHK8-00055k-TU for qemu-devel@nongnu.org; Fri, 30 May 2014 03:34:02 -0400 Received: from mail-pb0-x22b.google.com ([2607:f8b0:400e:c01::22b]:63369) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WqHK8-00055b-BN for qemu-devel@nongnu.org; Fri, 30 May 2014 03:33:56 -0400 Received: by mail-pb0-f43.google.com with SMTP id up15so1438430pbc.16 for ; Fri, 30 May 2014 00:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u775A0mebK5wBV0HAEL+AxEYoe6OyApsUQH5fYlig6k=; b=hprSW5N3gJN87XGqMfitqOev5XiSm7A8xrsbBvzxgT+WvxFjswlb4WrP1vpZd4kGZc +hpqNf0V+dsLFSqSBDAM0RD5MfrIjJIJ/4sORgm8DhO0MjzEzm8lfQ6ESzYiZeHZ0Eur 9NaGedEvXnLwgEQ69+d2CzkMYhpSUW9qilmT6Z82Ofp5/uoGYr4T0pKAxTHkmWLtUjay 0w1IflBGPUxdOi+HtIgUqw6yzzURgM8iQYrGn9iXOMycyllmV1P27klvCP+2mUeWNZKL mUM+iYCvbLIKcuPOXYILvAQJbZQoNVlSW1yegD27J3E2ig6PkJjtmT7FiOJpz3wPc/fS X0/g== X-Received: by 10.68.213.97 with SMTP id nr1mr15952326pbc.52.1401435235538; Fri, 30 May 2014 00:33:55 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ia2sm4822006pbb.32.2014.05.30.00.33.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 30 May 2014 00:33:55 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 30 May 2014 17:28:22 +1000 Message-Id: <1401434911-26992-8-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::22b Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v1 07/16] target-arm: Add HCR_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 35 +++++++++++++++++++++++++++++++++++ target-arm/helper.c | 27 +++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ef6a95d..b446478 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -184,6 +184,7 @@ typedef struct CPUARMState { MPU write buffer control. */ uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ + uint64_t hcr_el2; /* Hypervisor configuration register */ uint32_t ifsr_el2; /* Fault status registers. */ uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ @@ -526,6 +527,40 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) } } +#define HCR_VM (1ULL << 0) +#define HCR_SWIO (1ULL << 1) +#define HCR_PTW (1ULL << 2) +#define HCR_FMO (1ULL << 3) +#define HCR_IMO (1ULL << 4) +#define HCR_AMO (1ULL << 5) +#define HCR_VF (1ULL << 6) +#define HCR_VI (1ULL << 7) +#define HCR_VSE (1ULL << 8) +#define HCR_FB (1ULL << 9) +#define HCR_DC (1ULL << 12) +#define HCR_TWI (1ULL << 13) +#define HCR_TWE (1ULL << 14) +#define HCR_TID0 (1ULL << 15) +#define HCR_TID1 (1ULL << 16) +#define HCR_TID2 (1ULL << 17) +#define HCR_TID3 (1ULL << 18) +#define HCR_TSC (1ULL << 19) +#define HCR_TIDCP (1ULL << 20) +#define HCR_TACR (1ULL << 21) +#define HCR_TSW (1ULL << 22) +#define HCR_TPC (1ULL << 23) +#define HCR_TPU (1ULL << 24) +#define HCR_TTLB (1ULL << 25) +#define HCR_TVM (1ULL << 26) +#define HCR_TGE (1ULL << 27) +#define HCR_TDZ (1ULL << 28) +#define HCR_HCD (1ULL << 29) +#define HCR_TRVM (1ULL << 30) +#define HCR_RW (1ULL << 31) +#define HCR_CD (1ULL << 32) +#define HCR_ID (1ULL << 33) +#define HCR_RES0_MASK ((1ULL << 34) - 1) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target-arm/helper.c b/target-arm/helper.c index de5ee40..cf877ae 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2107,10 +2107,37 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, REGINFO_SENTINEL }; +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + uint64_t res0_mask = HCR_RES0_MASK; + + if (!arm_feature(env, ARM_FEATURE_EL3)) { + res0_mask &= ~HCR_HCD; + } + + /* Clear RES0 bits. */ + value &= res0_mask; + + if ((raw_read(env, ri) ^ value) & HCR_VM) { + /* Flush the TLB when turning VM on/off. */ + tlb_flush(CPU(cpu), 1); + } + raw_write(env, ri, value); +} + static const ARMCPRegInfo v8_el2_cp_reginfo[] = { + { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), + .writefn = hcr_write }, { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,