@@ -1464,6 +1464,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MI_CTR (0x300)
#define SPR_PERF1 (0x301)
#define SPR_RCPU_MI_RBA1 (0x301)
+#define SPR_POWER_UMMCR2 (0x301)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
@@ -1511,6 +1512,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
+#define SPR_POWER_MMCR2 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_POWER_MMCRA (0X312)
#define SPR_UPERF3 (0x313)
@@ -1563,6 +1565,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_440_ITV3 (0x377)
#define SPR_440_CCR1 (0x378)
#define SPR_DCRIPR (0x37B)
+#define SPR_POWER_MMCRS (0x37E)
#define SPR_PPR (0x380)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
@@ -7540,6 +7540,22 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
#endif
}
+static void gen_spr_power8_pmu(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR2, 0x00000000);
+ spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
+ &spr_read_ureg, &spr_write_ureg,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRS, 0x00000000);
+}
+
static void gen_spr_book3s_common(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@@ -7623,6 +7639,7 @@ static void init_proc_POWER(CPUPPCState *env, int version)
}
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_branch_control(env);
+ gen_spr_power8_pmu(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
This adds POWER8 specific PMU MMCR2/MMCRS SPRs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- target-ppc/cpu.h | 3 +++ target-ppc/translate_init.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+)