From patchwork Fri May 23 02:26:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 351699 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4081C14007B for ; Fri, 23 May 2014 12:30:19 +1000 (EST) Received: from localhost ([::1]:40596 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnfFR-0003Em-4H for incoming@patchwork.ozlabs.org; Thu, 22 May 2014 22:30:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnfCg-0006YE-8e for qemu-devel@nongnu.org; Thu, 22 May 2014 22:27:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WnfCU-0002Ue-Rf for qemu-devel@nongnu.org; Thu, 22 May 2014 22:27:26 -0400 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:52373) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnfCU-0002TH-09 for qemu-devel@nongnu.org; Thu, 22 May 2014 22:27:14 -0400 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 23 May 2014 12:27:04 +1000 Received: from d23relay05.au.ibm.com (d23relay05.au.ibm.com [9.190.235.152]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 685E72BB004A; Fri, 23 May 2014 12:27:04 +1000 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay05.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s4N25Q0l6357264; Fri, 23 May 2014 12:05:26 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s4N2R3Ux006033; Fri, 23 May 2014 12:27:03 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.190.163.12]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s4N2R35u006030; Fri, 23 May 2014 12:27:03 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.190.164.82]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 8E4F2A01C1; Fri, 23 May 2014 12:27:03 +1000 (EST) Received: from ka1.ozlabs.ibm.com (ka1.ozlabs.ibm.com [10.61.145.11]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id BF8C816AB65; Fri, 23 May 2014 12:27:02 +1000 (EST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Fri, 23 May 2014 12:26:52 +1000 Message-Id: <1400812018-23430-4-git-send-email-aik@ozlabs.ru> X-Mailer: git-send-email 1.9.rc0 In-Reply-To: <1400812018-23430-1-git-send-email-aik@ozlabs.ru> References: <1400812018-23430-1-git-send-email-aik@ozlabs.ru> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14052302-6102-0000-0000-000005A2A1F3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 202.81.31.145 Cc: Alexey Kardashevskiy , qemu-ppc@nongnu.org, Alexander Graf Subject: [Qemu-devel] [PATCH v3 3/9] target-ppc: Implement "compat" CPU option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr.c | 14 ++++++++++++++ target-ppc/cpu-qom.h | 2 ++ target-ppc/cpu.h | 11 +++++++++++ target-ppc/translate_init.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index aa17cae..5ea9640 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -210,6 +210,14 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, uint32_t gservers_prop[smt_threads * 2]; int index = ppc_get_vcpu_dt_id(cpu); + if (cpu->cpu_version) { + ret = fdt_setprop(fdt, offset, "cpu-version", + &cpu->cpu_version, sizeof(cpu->cpu_version)); + if (ret < 0) { + return ret; + } + } + /* Build interrupt servers and gservers properties */ for (i = 0; i < smt_threads; i++) { servers_prop[i] = cpu_to_be32(index + i); @@ -1289,6 +1297,12 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) kvmppc_set_papr(cpu); } + if (cpu->max_compat) { + if (ppc_set_compat(cpu, cpu->max_compat) < 0) { + exit(1); + } + } + xics_cpu_setup(spapr->icp, cpu); qemu_register_reset(spapr_cpu_reset, cpu); diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index 533de8f..e88e1da 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -84,6 +84,7 @@ typedef struct PowerPCCPUClass { * @env: #CPUPPCState * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too * @max_compat: Maximal supported logical PVR from the command line + * @cpu_version: Current logical PVR, zero if in "raw" mode * * A PowerPC CPU. */ @@ -95,6 +96,7 @@ struct PowerPCCPU { CPUPPCState env; int cpu_dt_id; uint32_t max_compat; + uint32_t cpu_version; }; static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b035e91..d3b8236 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1122,6 +1122,7 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); void ppc_store_msr (CPUPPCState *env, target_ulong value); void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); +int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version); /* Time-base and decrementer management */ #ifndef NO_CPU_IO_DEFS @@ -1338,6 +1339,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_LPCR (0x13E) #define SPR_BOOKE_DVC2 (0x13F) #define SPR_BOOKE_TSR (0x150) +#define SPR_PCR (0x152) #define SPR_BOOKE_TCR (0x154) #define SPR_BOOKE_TLB0PS (0x158) #define SPR_BOOKE_TLB1PS (0x159) @@ -2061,6 +2063,15 @@ enum { PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ }; +/* Processor Compatibility mask (PCR) */ +enum { + PCR_COMPAT_2_05 = 1ul << (63-62), + PCR_COMPAT_2_06 = 1ul << (63-61), + PCR_VEC_DIS = 1ul << (63-0), /* Vec. disable (bit NA since POWER8) */ + PCR_VSX_DIS = 1ul << (63-1), /* VSX disable (bit NA since POWER8) */ + PCR_TM_DIS = 1ul << (63-2), /* Trans. memory disable (POWER8) */ +}; + /*****************************************************************************/ static inline target_ulong cpu_read_xer(CPUPPCState *env) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 2e273dc..41afc5e 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7829,6 +7829,15 @@ static void init_proc_POWER7 (CPUPPCState *env) /* Can't find information on what this should be on reset. This * value is the one used by 74xx processors. */ vscr_init(env, 0x00010000); + + /* + * Register PCR to report POWERPC_EXCP_PRIV_REG instead of + * POWERPC_EXCP_INVAL_SPR. + */ + spr_register(env, SPR_PCR, "PCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + 0x00000000); } POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) @@ -8909,6 +8918,31 @@ static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) } } +int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version) +{ + int ret = 0; + CPUPPCState *env = &cpu->env; + + cpu->cpu_version = cpu_version; + + switch (cpu_version) { + case CPU_POWERPC_LOGICAL_2_05: + env->spr[SPR_PCR] = PCR_COMPAT_2_05; + break; + case CPU_POWERPC_LOGICAL_2_06: + env->spr[SPR_PCR] = PCR_COMPAT_2_06; + break; + case CPU_POWERPC_LOGICAL_2_06_PLUS: + env->spr[SPR_PCR] = PCR_COMPAT_2_06; + break; + default: + env->spr[SPR_PCR] = 0; + break; + } + + return ret; +} + static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) { ObjectClass *oc = (ObjectClass *)a;