From patchwork Wed May 21 06:20:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 350953 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 86EF11400A0 for ; Wed, 21 May 2014 16:23:26 +1000 (EST) Received: from localhost ([::1]:57167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wmzvw-0004ZN-5R for incoming@patchwork.ozlabs.org; Wed, 21 May 2014 02:23:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmztY-00009T-1l for qemu-devel@nongnu.org; Wed, 21 May 2014 02:21:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WmztJ-0005mH-FB for qemu-devel@nongnu.org; Wed, 21 May 2014 02:20:55 -0400 Received: from e23smtp05.au.ibm.com ([202.81.31.147]:47493) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmztI-0005lG-8u for qemu-devel@nongnu.org; Wed, 21 May 2014 02:20:41 -0400 Received: from /spool/local by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 21 May 2014 16:20:35 +1000 Received: from d23relay05.au.ibm.com (d23relay05.au.ibm.com [9.190.235.152]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id E26812BB0047; Wed, 21 May 2014 16:20:34 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay05.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s4L5wxGm45023356; Wed, 21 May 2014 15:58:59 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s4L6KYlN021110; Wed, 21 May 2014 16:20:34 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.190.163.12]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s4L6KYYb021101; Wed, 21 May 2014 16:20:34 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.190.164.82]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 1F582A011B; Wed, 21 May 2014 16:20:34 +1000 (EST) Received: from ka1.ozlabs.ibm.com (ka1.ozlabs.ibm.com [10.61.145.11]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 4E19C16AB74; Wed, 21 May 2014 16:20:33 +1000 (EST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Wed, 21 May 2014 16:20:24 +1000 Message-Id: <1400653228-31540-6-git-send-email-aik@ozlabs.ru> X-Mailer: git-send-email 1.9.rc0 In-Reply-To: <1400653228-31540-1-git-send-email-aik@ozlabs.ru> References: <1400653228-31540-1-git-send-email-aik@ozlabs.ru> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14052106-1396-0000-0000-000004E34B8C X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 202.81.31.147 Cc: Alexey Kardashevskiy , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf Subject: [Qemu-devel] [PATCH 5/9] target-ppc: Add POWER8 SPRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds helper which adds TAR/BESCRS/BESCRSU/BESCRR/BESCRRU/ EBBHR/EBBRR/BESCR/TFHAR/TFIAR/TEXASR/TEXASRU SPRs. This adds MMCR2/FSCR/MMCRS SPRs. Signed-off-by: Alexey Kardashevskiy --- target-ppc/cpu.h | 15 ++++++ target-ppc/translate_init.c | 123 ++++++++++++++++++++++++++++++++++---------- 2 files changed, 112 insertions(+), 26 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 262cf0f..72ed763 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1258,6 +1258,10 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_EIE (0x050) #define SPR_MPC_EID (0x051) #define SPR_MPC_NRI (0x052) +#define SPR_TFHAR (0x080) +#define SPR_TFIAR (0x081) +#define SPR_TEXASR (0x082) +#define SPR_TEXASRU (0x083) #define SPR_UCTRL (0x088) #define SPR_MPC_CMPA (0x090) #define SPR_MPC_CMPB (0x091) @@ -1270,6 +1274,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_CTRL (0x098) #define SPR_MPC_CMPE (0x098) #define SPR_MPC_CMPF (0x099) +#define SPR_FSCR (0x099) #define SPR_MPC_CMPG (0x09A) #define SPR_MPC_CMPH (0x09B) #define SPR_MPC_LCTRL1 (0x09C) @@ -1461,6 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_MI_CTR (0x300) #define SPR_PERF1 (0x301) #define SPR_RCPU_MI_RBA1 (0x301) +#define SPR_POWER_UMMCR2 (0x301) #define SPR_PERF2 (0x302) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) @@ -1500,6 +1506,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_MPC_MD_TW (0x30F) #define SPR_UPERF0 (0x310) #define SPR_UPERF1 (0x311) +#define SPR_POWER_MMCR2 (0x311) #define SPR_UPERF2 (0x312) #define SPR_MMCRA (0x312) #define SPR_UPERF3 (0x313) @@ -1519,11 +1526,18 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_UPERFF (0x31F) #define SPR_RCPU_MI_RA0 (0x320) #define SPR_MPC_MI_DBCAM (0x320) +#define SPR_BESCRS (0x320) #define SPR_RCPU_MI_RA1 (0x321) #define SPR_MPC_MI_DBRAM0 (0x321) +#define SPR_BESCRSU (0x321) #define SPR_RCPU_MI_RA2 (0x322) #define SPR_MPC_MI_DBRAM1 (0x322) +#define SPR_BESCRR (0x322) #define SPR_RCPU_MI_RA3 (0x323) +#define SPR_BESCRRU (0x323) +#define SPR_EBBHR (0x324) +#define SPR_EBBRR (0x325) +#define SPR_BESCR (0x326) #define SPR_RCPU_L2U_RA0 (0x328) #define SPR_MPC_MD_DBCAM (0x328) #define SPR_RCPU_L2U_RA1 (0x329) @@ -1542,6 +1556,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_440_ITV3 (0x377) #define SPR_440_CCR1 (0x378) #define SPR_DCRIPR (0x37B) +#define SPR_MMCRS (0x37E) #define SPR_PPR (0x380) #define SPR_750_GQR0 (0x390) #define SPR_440_DNV0 (0x390) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 3c37e93..d23fcc6 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7951,37 +7951,108 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } -static void init_proc_POWER8(CPUPPCState *env) +static void get_spr_power8_branch_control(CPUPPCState *env) { - gen_spr_ne_601(env); - gen_spr_7xx(env); - /* Time base */ - gen_tbl(env); - gen_spr_book3s_ids(env); - gen_spr_book3s_common(env); - gen_spr_amr(env); - gen_spr_book3s_vr(env); - gen_spr_book3s_lpar(env); - gen_spr_book3s_purr(env); - gen_spr_book3s_debug(env); - gen_spr_book3s_pmu(env); -#if !defined(CONFIG_USER_ONLY) - env->slb_nr = 32; -#endif /* !CONFIG_USER_ONLY */ - init_excp_POWER7(env); - env->dcache_line_size = 128; - env->icache_line_size = 128; - - /* Allocate hardware IRQ controller */ - ppcPOWER7_irq_init(env); - /* Can't find information on what this should be on reset. This - * value is the one used by 74xx processors. */ - vscr_init(env, 0x00010000); - spr_register(env, SPR_TAR, "TAR", &spr_read_generic, &spr_write_generic, &spr_read_generic, &spr_write_generic, 0x00000000); + + spr_register(env, SPR_BESCRS, "BESCRS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRSU, "BESCRSU", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRR, "BESCRR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BESCRRU, "BESCRRU", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_kvm(env, SPR_EBBHR, "EBBHR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_EBBHR, 0x00000000); + spr_register_kvm(env, SPR_EBBRR, "EBBRR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_EBBRR, 0x00000000); + spr_register_kvm(env, SPR_BESCR, "BESCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_BESCR, 0x00000000); +} + +static void get_spr_power8_tm(CPUPPCState *env) +{ + spr_register_kvm(env, SPR_TFHAR, "TFHAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TFHAR, 0x00000000); + spr_register_kvm(env, SPR_TFIAR, "TFIAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TFIAR, 0x00000000); + spr_register_kvm(env, SPR_TEXASR, "TEXASR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_TEXASR, 0x00000000); + spr_register(env, SPR_TEXASRU, "TEXASRU", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + +static void init_proc_POWER8(CPUPPCState *env) +{ + gen_spr_ne_601(env); + gen_spr_7xx(env); + /* Time base */ + gen_tbl(env); + gen_spr_book3s_ids(env); + gen_spr_book3s_common(env); + gen_spr_amr(env); + gen_spr_book3s_vr(env); + gen_spr_book3s_lpar(env); + gen_spr_book3s_purr(env); + gen_spr_book3s_debug(env); + gen_spr_book3s_pmu(env); +#if !defined(CONFIG_USER_ONLY) + env->slb_nr = 32; +#endif /* !CONFIG_USER_ONLY */ + init_excp_POWER7(env); + env->dcache_line_size = 128; + env->icache_line_size = 128; + + /* Allocate hardware IRQ controller */ + ppcPOWER7_irq_init(env); + /* Can't find information on what this should be on reset. This + * value is the one used by 74xx processors. */ + vscr_init(env, 0x00010000); + + get_spr_power8_branch_control(env); + get_spr_power8_tm(env); + spr_register(env, SPR_POWER_MMCR2, "MMCR2", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_kvm(env, SPR_POWER_UMMCR2, "UMMCR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR2, 0x00000000); + spr_register_kvm(env, SPR_FSCR, "FSCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_FSCR, 0x00000000); + spr_register_kvm(env, SPR_MMCRS, "MMCRS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCRS, 0x00000000); } POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)