From patchwork Wed May 21 06:20:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 350957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 757371400A0 for ; Wed, 21 May 2014 16:25:10 +1000 (EST) Received: from localhost ([::1]:57190 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wmzxc-0007c0-DL for incoming@patchwork.ozlabs.org; Wed, 21 May 2014 02:25:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wmzta-00009d-31 for qemu-devel@nongnu.org; Wed, 21 May 2014 02:21:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WmztM-0005oM-Tj for qemu-devel@nongnu.org; Wed, 21 May 2014 02:20:58 -0400 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:44090) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WmztM-0005mb-4V for qemu-devel@nongnu.org; Wed, 21 May 2014 02:20:44 -0400 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 21 May 2014 16:20:35 +1000 Received: from d23relay05.au.ibm.com (d23relay05.au.ibm.com [9.190.235.152]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 266BA3578053; Wed, 21 May 2014 16:20:34 +1000 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay05.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id s4L5wwvF66256896; Wed, 21 May 2014 15:58:58 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s4L6KXfr012112; Wed, 21 May 2014 16:20:33 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.190.163.12]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s4L6KXQA012099; Wed, 21 May 2014 16:20:33 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.190.164.82]) by ozlabs.au.ibm.com (Postfix) with ESMTP id E48C0A01D3; Wed, 21 May 2014 16:20:32 +1000 (EST) Received: from ka1.ozlabs.ibm.com (ka1.ozlabs.ibm.com [10.61.145.11]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 0FB9E16AB65; Wed, 21 May 2014 16:20:32 +1000 (EST) From: Alexey Kardashevskiy To: qemu-devel@nongnu.org Date: Wed, 21 May 2014 16:20:22 +1000 Message-Id: <1400653228-31540-4-git-send-email-aik@ozlabs.ru> X-Mailer: git-send-email 1.9.rc0 In-Reply-To: <1400653228-31540-1-git-send-email-aik@ozlabs.ru> References: <1400653228-31540-1-git-send-email-aik@ozlabs.ru> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14052106-6102-0000-0000-0000059EF8DA X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 202.81.31.145 Cc: Alexey Kardashevskiy , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf Subject: [Qemu-devel] [PATCH 3/9] target-ppc: Add POWER7 SPRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds TIR/SIAR/SDAR/MMCRA/MMCR0/MMCR1. This redefines UMMCRA (was MCCRA) and defines hypv version of if. Signed-off-by: Alexey Kardashevskiy --- target-ppc/cpu.h | 10 +++++++++- target-ppc/translate_init.c | 41 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 13eea19..262cf0f 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1371,6 +1371,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_BOOKE_GIVOR8 (0x1BB) #define SPR_BOOKE_GIVOR13 (0x1BC) #define SPR_BOOKE_GIVOR14 (0x1BD) +#define SPR_TIR (0x1BE) #define SPR_BOOKE_SPEFSCR (0x200) #define SPR_Exxx_BBEAR (0x201) #define SPR_Exxx_BBTAR (0x202) @@ -1463,7 +1464,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_PERF2 (0x302) #define SPR_RCPU_MI_RBA2 (0x302) #define SPR_MPC_MI_AP (0x302) -#define SPR_MMCRA (0x302) +#define SPR_UMMCRA (0x302) #define SPR_PERF3 (0x303) #define SPR_RCPU_MI_RBA3 (0x303) #define SPR_MPC_MI_EPN (0x303) @@ -1485,17 +1486,22 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_PERFB (0x30B) #define SPR_RCPU_L2U_RBA3 (0x30B) #define SPR_MPC_MD_EPN (0x30B) +#define SPR_POWER_UMMCR0 (0x30B) #define SPR_PERFC (0x30C) #define SPR_MPC_MD_TWB (0x30C) +#define SPR_BOOK3S_SIAR (0x30C) +#define SPR_BOOK3S_SDAR (0x30D) #define SPR_PERFD (0x30D) #define SPR_MPC_MD_TWC (0x30D) #define SPR_PERFE (0x30E) #define SPR_MPC_MD_RPN (0x30E) +#define SPR_POWER_UMMCR1 (0x30E) #define SPR_PERFF (0x30F) #define SPR_MPC_MD_TW (0x30F) #define SPR_UPERF0 (0x310) #define SPR_UPERF1 (0x311) #define SPR_UPERF2 (0x312) +#define SPR_MMCRA (0x312) #define SPR_UPERF3 (0x313) #define SPR_UPERF4 (0x314) #define SPR_UPERF5 (0x315) @@ -1505,9 +1511,11 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_UPERF9 (0x319) #define SPR_UPERFA (0x31A) #define SPR_UPERFB (0x31B) +#define SPR_POWER_MMCR0 (0x31B) #define SPR_UPERFC (0x31C) #define SPR_UPERFD (0x31D) #define SPR_UPERFE (0x31E) +#define SPR_POWER_MMCR1 (0x31E) #define SPR_UPERFF (0x31F) #define SPR_RCPU_MI_RA0 (0x320) #define SPR_MPC_MI_DBCAM (0x320) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index e9c37fa..b92b447 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7687,6 +7687,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_pir, 0x00000000); + + spr_register(env, SPR_TIR, "TIR", + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); } static void gen_spr_book3s_purr(CPUPPCState *env) @@ -7711,16 +7716,20 @@ static void gen_spr_book3s_debug(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_cfar, &spr_write_cfar, 0x00000000); + spr_register_kvm(env, SPR_BOOK3S_SIAR, "SIAR", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SIAR, 0x00000000); + spr_register_kvm(env, SPR_BOOK3S_SDAR, "SDAR", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_SDAR, 0x00000000); #endif } static void gen_spr_book3s_pmu(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) - spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_PMC5, "SPR_PMC5", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -7729,6 +7738,30 @@ static void gen_spr_book3s_pmu(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_PMC6, 0x00000000); + spr_register(env, SPR_MMCRA, "MMCRA", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_kvm(env, SPR_UMMCRA, "UMMCRA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCRA, 0x00000000); + spr_register(env, SPR_POWER_MMCR0, "MMCR0", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_kvm(env, SPR_POWER_UMMCR0, "UMMCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR0, 0x00000000); + spr_register(env, SPR_POWER_MMCR1, "MMCR1", + &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_kvm(env, SPR_POWER_UMMCR1, "UMMCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_MMCR1, 0x00000000); #endif }