From patchwork Tue May 13 16:15:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabian Aggeler X-Patchwork-Id: 348449 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D0BE0140087 for ; Wed, 14 May 2014 02:18:37 +1000 (EST) Received: from localhost ([::1]:46397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFPX-0008NB-LK for incoming@patchwork.ozlabs.org; Tue, 13 May 2014 12:18:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOr-0007D5-U4 for qemu-devel@nongnu.org; Tue, 13 May 2014 12:18:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOh-0005WR-B2 for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:53 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:24924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOh-0005Vy-4x for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:43 -0400 Received: from CAS10.d.ethz.ch (172.31.38.210) by edge10.ethz.ch (82.130.75.186) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 13 May 2014 18:17:41 +0200 Received: from qemubox.inf.ethz.ch (192.33.93.3) by cas10.d.ethz.ch (172.31.38.210) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 13 May 2014 18:17:41 +0200 From: Fabian Aggeler To: Date: Tue, 13 May 2014 18:15:47 +0200 Message-ID: <1399997768-32014-3-git-send-email-aggelerf@ethz.ch> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 X-Originating-IP: [192.33.93.3] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 82.130.75.186 Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Fabian Aggeler , peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH v2 02/23] target-arm: move SCR into Security Extensions register list X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Sergey Fedorov Define a new ARM CP register info list for the Security Extension feature. Register that list only for ARM cores with Security Extension support. Moving SCR into Security Extension register group. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/helper.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3be917c..7898f40 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -768,9 +768,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), .resetvalue = 0 }, - { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), - .resetvalue = 0, }, { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, @@ -2087,6 +2084,15 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush(CPU(cpu), 1); } +static const ARMCPRegInfo tz_cp_reginfo[] = { +#ifndef CONFIG_USER_ONLY + { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), + .resetvalue = 0, }, +#endif + REGINFO_SENTINEL +}; + static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) { /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, @@ -2364,6 +2370,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_SECURITY_EXTENSIONS)) { + define_arm_cp_regs(cpu, tz_cp_reginfo); + } /* Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=0 to be writes-ignored, whereas for other cores they should * be read-only (ie write causes UNDEF exception).