From patchwork Wed Apr 30 16:48:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Eduardo Habkost X-Patchwork-Id: 344231 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7FDB8140083 for ; Thu, 1 May 2014 03:03:33 +1000 (EST) Received: from localhost ([::1]:58018 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfXut-0002ka-Dv for incoming@patchwork.ozlabs.org; Wed, 30 Apr 2014 13:03:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfXmy-00069P-8v for qemu-devel@nongnu.org; Wed, 30 Apr 2014 12:55:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WfXms-000534-3K for qemu-devel@nongnu.org; Wed, 30 Apr 2014 12:55:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:2622) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfXmr-00052z-SH for qemu-devel@nongnu.org; Wed, 30 Apr 2014 12:55:14 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s3UGnehd011563 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 30 Apr 2014 12:49:40 -0400 Received: from localhost (ovpn-113-106.phx2.redhat.com [10.3.113.106]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s3UGndWI022481; Wed, 30 Apr 2014 12:49:39 -0400 From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Wed, 30 Apr 2014 13:48:45 -0300 Message-Id: <1398876525-28831-19-git-send-email-ehabkost@redhat.com> In-Reply-To: <1398876525-28831-1-git-send-email-ehabkost@redhat.com> References: <1398876525-28831-1-git-send-email-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-MIME-Autoconverted: from 8bit to quoted-printable by mx1.redhat.com id s3UGnehd011563 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: Marcelo Tosatti , Paolo Bonzini , Igor Mammedov , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v4 18/18] target-i386: support "invariant tsc" flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Marcelo Tosatti Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation: 17.13.1 Invariant TSC The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor’s support for invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is the architectural behavior moving forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition or access to a platform resource. Signed-off-by: Marcelo Tosatti [ehabkost: redo feature filtering to use .tcg_features] [ehabkost: add CPUID_APM_INVTSC macro, add it to .unmigratable_flags] Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 25 +++++++++++++++++++++++++ target-i386/cpu.h | 4 ++++ 2 files changed, 29 insertions(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 9ef27fc..90757ad 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -262,6 +262,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; +static const char *cpuid_apm_edx_feature_name[] = { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + "invtsc", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -329,6 +340,7 @@ static const char *cpuid_7_0_ebx_feature_name[] = { CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ +#define TCG_APM_FEATURES 0 typedef struct FeatureWordInfo { @@ -384,6 +396,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_reg = R_EBX, .tcg_features = TCG_7_0_EBX_FEATURES, }, + [FEAT_8000_0007_EDX] = { + .feat_names = cpuid_apm_edx_feature_name, + .cpuid_eax = 0x80000007, + .cpuid_reg = R_EDX, + .tcg_features = TCG_APM_FEATURES, + .unmigratable_flags = CPUID_APM_INVTSC, + }, }; typedef struct X86RegisterInfo32 { @@ -2392,6 +2411,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \ (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE); break; + case 0x80000007: + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = env->features[FEAT_8000_0007_EDX]; + break; case 0x80000008: /* virtual & phys address size in low 2 bytes. */ /* XXX: This value must match the one used in the MMU code. */ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2a22a7d..1bb98e6 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -398,6 +398,7 @@ typedef enum FeatureWord { FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ + FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */ @@ -557,6 +558,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +/* CPUID[0x80000007].EDX flags: */ +#define CPUID_APM_INVTSC (1U << 8) + #define CPUID_VENDOR_SZ 12 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */