From patchwork Fri Apr 18 14:50:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 340362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 948741400F8 for ; Sat, 19 Apr 2014 02:00:20 +1000 (EST) Received: from localhost ([::1]:38359 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WbAId-0004Qb-GA for incoming@patchwork.ozlabs.org; Fri, 18 Apr 2014 11:01:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WbA8p-0006aK-ID for qemu-devel@nongnu.org; Fri, 18 Apr 2014 10:52:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WbA8d-0000ga-2W for qemu-devel@nongnu.org; Fri, 18 Apr 2014 10:51:47 -0400 Received: from mail-qa0-x22b.google.com ([2607:f8b0:400d:c00::22b]:44508) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WbA8c-0000ew-NH; Fri, 18 Apr 2014 10:51:34 -0400 Received: by mail-qa0-f43.google.com with SMTP id j15so1643477qaq.30 for ; Fri, 18 Apr 2014 07:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0dPPzj7FMUb2qKCNgLLu/U5cQNooSiKfxE+kt/9YxIY=; b=xrsqfQ+jN6z3tl8LsbB731/LnZ83EbCJDI59vy6KN51NIN/8Ybrd8ViLp9vN6KH8Fz 3IH7VdVg2AZ/uULxhil/eOtNHbfoj8s9SWQLnbq86b+6utjiSK5s2ZHffh2+S0QCThJn 7+Tayjeamg0oaFmvUW+IlKlPdqGYH5z21XA0d2k6U3/gpZ7MdTrzi6BJqzUAsKpuB4GN sWgp2ryJCksKYVLLXvi+Z2TYZroiZvidYGr1pMFaTosa+17huhbPWGsu4aw5QdNN3Wq9 sT70HpZx4sygBC80QVx0pTT3KgBNDm8Cj5N/RUkUj2V5y465oR0uopn4m5NC9dIlweuS Dv3g== X-Received: by 10.140.25.247 with SMTP id 110mr18113314qgt.83.1397832694188; Fri, 18 Apr 2014 07:51:34 -0700 (PDT) Received: from tmusta-sc.rchland.ibm.com (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id u59sm37020178qga.8.2014.04.18.07.51.32 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 18 Apr 2014 07:51:33 -0700 (PDT) From: Tom Musta To: qemu-devel@nongnu.org Date: Fri, 18 Apr 2014 09:50:33 -0500 Message-Id: <1397832641-10254-30-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1397832641-10254-1-git-send-email-tommusta@gmail.com> References: <1397832641-10254-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c00::22b Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [PATCH 29/37] target-ppc: Introduce DFP Convert to Long/Extended X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add emulation of the PowerPC Convert to DFP Long (dctdp[.]) and Convert to DFP Extended (dctqpq[.]) instructions. Signed-off-by: Tom Musta --- target-ppc/dfp_helper.c | 35 +++++++++++++++++++++++++++++++++++ target-ppc/helper.h | 2 ++ target-ppc/translate.c | 4 ++++ 3 files changed, 41 insertions(+), 0 deletions(-) diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c index 5c60492..a719797 100644 --- a/target-ppc/dfp_helper.c +++ b/target-ppc/dfp_helper.c @@ -286,6 +286,15 @@ static void dfp_check_for_VXSNAN(struct PPC_DFP *dfp) } } +static void dfp_check_for_VXSNAN_and_convert_to_QNaN(struct PPC_DFP *dfp) +{ + if (decNumberIsSNaN(&dfp->t)) { + dfp->t.bits &= ~DECSNAN; + dfp->t.bits |= DECNAN; + dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXSNAN, FP_VE); + } +} + static void dfp_check_for_VXISI(struct PPC_DFP *dfp, int testForSameSign) { if (dfp->context.status & DEC_Invalid_operation) { @@ -845,3 +854,29 @@ PPC_DFP_PostProc RINTN_PPs[] = { DFP_HELPER_RINT(drintn, RINTN_PPs, 64) DFP_HELPER_RINT(drintnq, RINTN_PPs, 128) + +void helper_dctdp(CPUPPCState *env, uint64_t *t, uint64_t *b) +{ + struct PPC_DFP dfp; + uint32_t b_short = *b; + dfp_prepare_decimal64(&dfp, 0, 0, env); + decimal32ToNumber((decimal32 *)&b_short, &dfp.t); + decimal64FromNumber((decimal64 *)t, &dfp.t, &dfp.context); + dfp_set_FPRF_from_FRT(&dfp); +} + +PPC_DFP_PostProc CTQPQ_PPs[] = { + dfp_check_for_VXSNAN_and_convert_to_QNaN, + dfp_set_FPRF_from_FRT, +}; + +void helper_dctqpq(CPUPPCState *env, uint64_t *t, uint64_t *b) +{ + struct PPC_DFP dfp; + dfp_prepare_decimal128(&dfp, 0, 0, env); + decimal64ToNumber((decimal64 *)b, &dfp.t); + dfp_run_post_processors(&dfp, CTQPQ_PPs, ARRAY_SIZE(CTQPQ_PPs)); + decimal128FromNumber((decimal128 *)&dfp.t64, &dfp.t, &dfp.context); + t[0] = dfp.t64[HI_IDX]; + t[1] = dfp.t64[LO_IDX]; +} diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 2ef18c2..a99ca1c 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -648,4 +648,6 @@ DEF_HELPER_5(drintx, void, env, fprp, fprp, i32, i32) DEF_HELPER_5(drintxq, void, env, fprp, fprp, i32, i32) DEF_HELPER_5(drintn, void, env, fprp, fprp, i32, i32) DEF_HELPER_5(drintnq, void, env, fprp, fprp, i32, i32) +DEF_HELPER_3(dctdp, void, env, fprp, fprp) +DEF_HELPER_3(dctqpq, void, env, fprp, fprp) #include "exec/def-helper.h" diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 65b1503..da70c8d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8386,6 +8386,8 @@ GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC) GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC) GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC) GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC) +GEN_DFP_T_B_Rc(dctdp) +GEN_DFP_T_B_Rc(dctqpq) /*** SPE extension ***/ /* Register moves */ @@ -11343,6 +11345,8 @@ GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03), GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03), GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07), GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07), +GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08), +GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08), #undef GEN_SPE #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)