From patchwork Wed Apr 16 16:47:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 339660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id ADBFE140096 for ; Thu, 17 Apr 2014 02:49:06 +1000 (EST) Received: from localhost ([::1]:55663 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WaT1E-0007Yh-Gm for incoming@patchwork.ozlabs.org; Wed, 16 Apr 2014 12:49:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WaT0X-0006GM-UU for qemu-devel@nongnu.org; Wed, 16 Apr 2014 12:48:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WaT0S-0007zb-KR for qemu-devel@nongnu.org; Wed, 16 Apr 2014 12:48:21 -0400 Received: from mail-qc0-x22d.google.com ([2607:f8b0:400d:c01::22d]:43772) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WaT0S-0007zX-Fq for qemu-devel@nongnu.org; Wed, 16 Apr 2014 12:48:16 -0400 Received: by mail-qc0-f173.google.com with SMTP id r5so12206108qcx.18 for ; Wed, 16 Apr 2014 09:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=5B/XiW+2AwwyP2sDFrZplB1hejQioHmYHULqcZqzvMM=; b=v4b1kZhlWvhs0AYuIshMbMNEUosx0HDyOgd4vz/B+lrsc7ttJsSiwfACU2GNBFgsJW xizNuDwubEcVwF5HzMSh0w+Iz/0eV/w5X8o2Sym0gHNjoNAtqPpkebPzgyzjV+azZXPw OE/JMHHmjXivVIdB3AQrnecFw1DwMCURfLsd9aqVKSyr1o1cYmOf8WWZ+/3drsgHrT2M cRHBzrrLdvHNr/DnQX7jeISXA7sJtKDATl54vBpH4XummZB1G8VDWhF1dejNqgALkZwm XqrRTLMuxTpr54KdmsUYC8Siwkw1LgvpIsEAfeiWuxDfQtEG/ex/RJOJh3r0D09kqQhI SRZQ== X-Received: by 10.140.40.47 with SMTP id w44mr3805324qgw.112.1397666895920; Wed, 16 Apr 2014 09:48:15 -0700 (PDT) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id s13sm44379276qag.19.2014.04.16.09.48.14 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Apr 2014 09:48:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 Apr 2014 09:47:28 -0700 Message-Id: <1397666860-26946-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1397666860-26946-1-git-send-email-rth@twiddle.net> References: <1397666860-26946-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22d Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH for-2.1 02/14] tcg: Use "unspecified behavior" for shifts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Change the definition such that shifts are not allowed to crash for any input. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/README | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/README b/tcg/README index f178212..776e925 100644 --- a/tcg/README +++ b/tcg/README @@ -36,6 +36,12 @@ or a memory location which is stored in a register outside QEMU TBs A TCG "basic block" corresponds to a list of instructions terminated by a branch instruction. +An operation with "undefined behavior" may result in a crash. + +An operation with "unspecified behavior" shall not crash. However, +the result may be one of several possibilities so may be considered +an "undefined result". + 3) Intermediate representation 3.1) Introduction @@ -239,23 +245,25 @@ t0=t1|~t2 * shl_i32/i64 t0, t1, t2 -t0=t1 << t2. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * shr_i32/i64 t0, t1, t2 -t0=t1 >> t2 (unsigned). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * sar_i32/i64 t0, t1, t2 -t0=t1 >> t2 (signed). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * rotl_i32/i64 t0, t1, t2 -Rotation of t2 bits to the left. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +Rotation of t2 bits to the left. +Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * rotr_i32/i64 t0, t1, t2 -Rotation of t2 bits to the right. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +Rotation of t2 bits to the right. +Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) ********* Misc