From patchwork Mon Mar 31 21:03:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 335629 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BFDF7140078 for ; Tue, 1 Apr 2014 10:07:33 +1100 (EST) Received: from localhost ([::1]:51334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WUjQS-0007Sg-1x for incoming@patchwork.ozlabs.org; Mon, 31 Mar 2014 17:07:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WUjNm-0004KH-LT for qemu-devel@nongnu.org; Mon, 31 Mar 2014 17:04:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WUjNd-0003iB-6a for qemu-devel@nongnu.org; Mon, 31 Mar 2014 17:04:38 -0400 Received: from mail-qc0-x22c.google.com ([2607:f8b0:400d:c01::22c]:42971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WUjNd-0003i6-2b; Mon, 31 Mar 2014 17:04:29 -0400 Received: by mail-qc0-f172.google.com with SMTP id i8so9781907qcq.31 for ; Mon, 31 Mar 2014 14:04:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ws559iGCxzAmAbNNfxxiVBZjZDagyJf9c/OwivAaeJw=; b=a0iCydS2LEryMFsy+aBZTlpvxgApqjsj+C+Bnyw74lIi2LnVvCrt8cvNu23kAM4Kei T9JX3CCzqAdhI7VvAYP3Ibc0AxtUq9CVh2jXbie+lurN2d+k1UqUBn3fnzNGe/sqYizo UPldpZYn6bm1tbol3Mnvmip25OoqWoiSX+GnkukiPzLmeENmFS+2SJuNCQeps8kKfgkS QUh8X1ZYjM3tsC736whWZ7A5T9Xc6MJxpGGYsfYOnWCk5R4M3987Po3Ec6iOhUenU2Os knbmVdLYn3QBdjTGNz+LOrmUtLSFffKt/q+R3P4WqhhGMY4u/rX2BOM9IoOXV+mh7Kmt q9xg== X-Received: by 10.224.20.72 with SMTP id e8mr5581875qab.86.1396299868609; Mon, 31 Mar 2014 14:04:28 -0700 (PDT) Received: from tmusta-sc.rchland.ibm.com (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id w67sm14626836qge.12.2014.03.31.14.04.26 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 31 Mar 2014 14:04:27 -0700 (PDT) From: Tom Musta To: qemu-devel@nongnu.org Date: Mon, 31 Mar 2014 16:03:58 -0500 Message-Id: <1396299843-7313-5-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396299843-7313-1-git-send-email-tommusta@gmail.com> References: <1396299843-7313-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22c Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V2 PATCH 4/9] target-ppc: Correct LE Host Inversion of Lower VSRs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This change properly orders the doublewords of the VSRs 0-31. Because these registers are constructed from separate doublewords, they must be inverted on Little Endian hosts. The inversion is performed both when the VSR is read and when it is written. Signed-off-by: Tom Musta Tested-by: Tom Musta --- target-ppc/fpu_helper.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index d79aae9..9fc7dd8 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1793,8 +1793,8 @@ typedef union _ppc_vsr_t { static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - vsr->f64[0] = env->fpr[n]; - vsr->u64[1] = env->vsr[n]; + vsr->VsrD(0) = env->fpr[n]; + vsr->VsrD(1) = env->vsr[n]; } else { vsr->u64[0] = env->avr[n-32].u64[0]; vsr->u64[1] = env->avr[n-32].u64[1]; @@ -1804,8 +1804,8 @@ static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - env->fpr[n] = vsr->f64[0]; - env->vsr[n] = vsr->u64[1]; + env->fpr[n] = vsr->VsrD(0); + env->vsr[n] = vsr->VsrD(1); } else { env->avr[n-32].u64[0] = vsr->u64[0]; env->avr[n-32].u64[1] = vsr->u64[1];