From patchwork Tue Mar 25 18:22:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 333650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 67BF014007B for ; Wed, 26 Mar 2014 05:23:59 +1100 (EST) Received: from localhost ([::1]:43485 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSW0z-0007I2-Ao for incoming@patchwork.ozlabs.org; Tue, 25 Mar 2014 14:23:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSW0F-00070A-Be for qemu-devel@nongnu.org; Tue, 25 Mar 2014 14:23:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WSW09-0004C7-Fg for qemu-devel@nongnu.org; Tue, 25 Mar 2014 14:23:11 -0400 Received: from mail-ee0-x233.google.com ([2a00:1450:4013:c00::233]:35726) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSW09-0004BG-8z for qemu-devel@nongnu.org; Tue, 25 Mar 2014 14:23:05 -0400 Received: by mail-ee0-f51.google.com with SMTP id c13so772134eek.24 for ; Tue, 25 Mar 2014 11:23:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M+sNBv+nKZ/qjKfhE5ifGxHjjs1gv62YV1e0LDPFXu0=; b=aLYOaSbXuFKLEbh6xMYHSL5duD7qAVQ1RhhDm9pLZJgt6/+6h9+upJCnT3cev5B/ll MXJAsWC1+/D2jdRyfeNoUR78YiKtJnvXMlENHc08xURIRGv6YVFhMYNWjt8FZB6cp6s/ +L2VsB+WlQyBk+cPli7cTDao2HII8/pe8toiUsrWwx39ReP3udhSG1ciwHOIyrAmmoji ptKeHEgxTeO5JX6azd+ClaQw67gzx7efn2QjgyrXz4+TOPoFl+4wQs4QU+XBW9mkYNX7 3ML9PqVd1Pf0eVGcKc8pu7wZHxo9k3qJ0GG7+laGQBdHNf/k1cuZ4+fb1bmD5O4p25Rs sd0g== X-Received: by 10.15.75.9 with SMTP id k9mr72250eey.110.1395771784423; Tue, 25 Mar 2014 11:23:04 -0700 (PDT) Received: from sark.local (host151-4-dynamic.21-79-r.retail.telecomitalia.it. [79.21.4.151]) by mx.google.com with ESMTPSA id x45sm41766822eeu.23.2014.03.25.11.23.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Mar 2014 11:23:03 -0700 (PDT) From: Beniamino Galvani To: qemu-devel@nongnu.org Date: Tue, 25 Mar 2014 19:22:07 +0100 Message-Id: <1395771730-16882-5-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395771730-16882-1-git-send-email-b.galvani@gmail.com> References: <1395771730-16882-1-git-send-email-b.galvani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c00::233 Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Subject: [Qemu-devel] [PATCH v5 4/7] allwinner-a10-pit: use level triggered interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite --- hw/timer/allwinner-a10-pit.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 696b7d9..5aa78a9 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -19,6 +19,15 @@ #include "sysemu/sysemu.h" #include "hw/timer/allwinner-a10-pit.h" +static void a10_pit_update_irq(AwA10PITState *s) +{ + int i; + + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); + } +} + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -74,9 +83,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -178,6 +189,8 @@ static void a10_pit_reset(DeviceState *dev) s->irq_enable = 0; s->irq_status = 0; + a10_pit_update_irq(s); + for (i = 0; i < 6; i++) { s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] = 0; @@ -203,7 +216,7 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i]); s->control[i] &= ~AW_A10_PIT_TIMER_EN; } - qemu_irq_pulse(s->irq[i]); + a10_pit_update_irq(s); } }