diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2719c08..7082041 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1452,54 +1452,81 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_MPC_MI_CTR        (0x300)
 #define SPR_PERF1             (0x301)
 #define SPR_RCPU_MI_RBA1      (0x301)
+#define SPR_BOOK3S_UMMCR2     (0x301)
 #define SPR_PERF2             (0x302)
 #define SPR_RCPU_MI_RBA2      (0x302)
 #define SPR_MPC_MI_AP         (0x302)
-#define SPR_MMCRA             (0x302)
+#define SPR_BOOK3S_UMMCRA     (0x302)
 #define SPR_PERF3             (0x303)
 #define SPR_RCPU_MI_RBA3      (0x303)
 #define SPR_MPC_MI_EPN        (0x303)
+#define SPR_BOOK3S_UPMC1      (0x303)
 #define SPR_PERF4             (0x304)
+#define SPR_BOOK3S_UPMC2      (0x304)
 #define SPR_PERF5             (0x305)
 #define SPR_MPC_MI_TWC        (0x305)
+#define SPR_BOOK3S_UPMC3      (0x305)
 #define SPR_PERF6             (0x306)
 #define SPR_MPC_MI_RPN        (0x306)
+#define SPR_BOOK3S_UPMC4      (0x306)
 #define SPR_PERF7             (0x307)
+#define SPR_BOOK3S_UPMC5      (0x307)
 #define SPR_PERF8             (0x308)
 #define SPR_RCPU_L2U_RBA0     (0x308)
 #define SPR_MPC_MD_CTR        (0x308)
+#define SPR_BOOK3S_UPMC6      (0x308)
 #define SPR_PERF9             (0x309)
 #define SPR_RCPU_L2U_RBA1     (0x309)
 #define SPR_MPC_MD_CASID      (0x309)
+#define SPR_BOOK3S_UPMC7      (0x309)
 #define SPR_PERFA             (0x30A)
 #define SPR_RCPU_L2U_RBA2     (0x30A)
 #define SPR_MPC_MD_AP         (0x30A)
+#define SPR_BOOK3S_UPMC8      (0x30A)
 #define SPR_PERFB             (0x30B)
 #define SPR_RCPU_L2U_RBA3     (0x30B)
 #define SPR_MPC_MD_EPN        (0x30B)
+#define SPR_BOOK3S_UMMCR0     (0x30B)
 #define SPR_PERFC             (0x30C)
 #define SPR_MPC_MD_TWB        (0x30C)
+#define SPR_BOOK3S_USIAR      (0x30C)
 #define SPR_PERFD             (0x30D)
 #define SPR_MPC_MD_TWC        (0x30D)
+#define SPR_BOOK3S_USDAR      (0x30D)
 #define SPR_PERFE             (0x30E)
 #define SPR_MPC_MD_RPN        (0x30E)
+#define SPR_BOOK3S_UMMCR1     (0x30E)
 #define SPR_PERFF             (0x30F)
 #define SPR_MPC_MD_TW         (0x30F)
 #define SPR_UPERF0            (0x310)
 #define SPR_UPERF1            (0x311)
+#define SPR_BOOK3S_MMCR2      (0x311)
 #define SPR_UPERF2            (0x312)
+#define SPR_BOOK3S_MMCRA      (0x312)
 #define SPR_UPERF3            (0x313)
+#define SPR_BOOK3S_PMC1       (0x313)
 #define SPR_UPERF4            (0x314)
+#define SPR_BOOK3S_PMC2       (0x314)
 #define SPR_UPERF5            (0x315)
+#define SPR_BOOK3S_PMC3       (0x315)
 #define SPR_UPERF6            (0x316)
+#define SPR_BOOK3S_PMC4       (0x316)
 #define SPR_UPERF7            (0x317)
+#define SPR_BOOK3S_PMC5       (0x317)
 #define SPR_UPERF8            (0x318)
+#define SPR_BOOK3S_PMC6       (0x318)
 #define SPR_UPERF9            (0x319)
+#define SPR_BOOK3S_PMC7       (0x319)
 #define SPR_UPERFA            (0x31A)
+#define SPR_BOOK3S_PMC8       (0x31A)
 #define SPR_UPERFB            (0x31B)
+#define SPR_BOOK3S_MMCR0      (0x31B)
 #define SPR_UPERFC            (0x31C)
+#define SPR_BOOK3S_SIAR       (0x31C)
 #define SPR_UPERFD            (0x31D)
+#define SPR_BOOK3S_SDAR       (0x31D)
 #define SPR_UPERFE            (0x31E)
+#define SPR_BOOK3S_MMCR1      (0x31E)
 #define SPR_UPERFF            (0x31F)
 #define SPR_RCPU_MI_RA0       (0x320)
 #define SPR_MPC_MI_DBCAM      (0x320)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d07e186..273e37d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6629,10 +6629,128 @@ static int check_pow_970 (CPUPPCState *env)
     return 0;
 }
 
+/* SPR common to all book3s implementations */
+static void gen_spr_book3s (CPUPPCState *env)
+{
+    /* Breakpoints */
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_DABR, "DABR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_DABR, 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_IABR, "IABR",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_read_generic, &spr_write_generic,
+                 0x00000000);
+
+    /* Performance monitors */
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_MMCR0, "MMCR0",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_MMCR0, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_MMCR1, "MMCR1",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_MMCR1, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC1, "PMC1",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC1, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC2, "PMC2",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC2, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC3, "PMC3",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC3, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC4, "PMC4",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC4, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC5, "PMC5",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC5, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_PMC6, "PMC6",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_PMC6, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_SIAR, "SIAR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     KVM_REG_PPC_SIAR, 0x00000000);
+    /* XXX : not implemented */
+    spr_register_kvm(env, SPR_BOOK3S_SDAR, "SDAR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     KVM_REG_PPC_SDAR, 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UMMCR0, "UMMCR0",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UMMCR1, "UMMCR1",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC1, "UPMC1",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC2, "UPMC2",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC3, "UPMC3",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC4, "UPMC4",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC5, "UPMC5",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_UPMC6, "UPMC6",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_USIAR, "USIAR",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+    /* XXX : not implemented */
+    spr_register(env, SPR_BOOK3S_USDAR, "USDAR",
+                 &spr_read_ureg, SPR_NOACCESS,
+                 &spr_read_ureg, SPR_NOACCESS,
+                 0x00000000);
+}
+
 static void init_proc_970 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6712,7 +6830,7 @@ static int check_pow_970FX (CPUPPCState *env)
 static void init_proc_970FX (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6804,7 +6922,7 @@ static int check_pow_970MP (CPUPPCState *env)
 static void init_proc_970MP (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6882,7 +7000,7 @@ POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
 static void init_proc_power5plus(CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Hardware implementation registers */
@@ -6972,7 +7090,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
 static void init_proc_POWER7 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
-    gen_spr_7xx(env);
+    gen_spr_book3s(env);
     /* Time base */
     gen_tbl(env);
     /* Processor identification */
@@ -6998,18 +7116,11 @@ static void init_proc_POWER7 (CPUPPCState *env)
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_DSCR, 0x00000000);
-    spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+    spr_register_kvm(env, SPR_BOOK3S_MMCRA, "SPR_MMCRA",
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_MMCRA, 0x00000000);
-    spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
-                     SPR_NOACCESS, SPR_NOACCESS,
-                     &spr_read_generic, &spr_write_generic,
-                     KVM_REG_PPC_PMC5, 0x00000000);
-    spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
-                     SPR_NOACCESS, SPR_NOACCESS,
-                     &spr_read_generic, &spr_write_generic,
-                     KVM_REG_PPC_PMC6, 0x00000000);
+
 #endif /* !CONFIG_USER_ONLY */
     gen_spr_amr(env);
     /* XXX : not implemented */
