From patchwork Thu Mar 20 21:25:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 332399 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A80A62C00AB for ; Fri, 21 Mar 2014 08:26:55 +1100 (EST) Received: from localhost ([::1]:49521 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkUH-0000I5-Kq for incoming@patchwork.ozlabs.org; Thu, 20 Mar 2014 17:26:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33814) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTZ-0008Us-F0 for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQkTT-0003uz-Vp for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:09 -0400 Received: from mail-ee0-x22b.google.com ([2a00:1450:4013:c00::22b]:49115) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTT-0003ur-Oe for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:03 -0400 Received: by mail-ee0-f43.google.com with SMTP id e53so1146316eek.30 for ; Thu, 20 Mar 2014 14:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/WN5f3sACGL4lz9lRixS0l7YqJSqE8AAl3YDkYJFQxw=; b=eHf2vBCQi6lHU+oyNy3EnXaLP3Hn7AP/3uWxTY+xfY6X+wmmawYrOdN7LlpEN/vB5d Hrrj4acTl39b1Cb3d5yYPoMohl0aWmbpRyElbrbEc2XGwMeLHNXZPdieFfPFw68kgjw3 fDfRk89WR1Y8tr/8I2BqXL2dU+x43NyvhYPfrNFheU/8xAWOwJzcZ9o1Y0rVGXHobGWG o5yoUMr++Wgx4QF0VWihqbLkraK/ES2HnHvuC+yyNVaHGNCULh7pWIFK3gN2F4KMZaZb JQfVHcFM5omeKFU5D4ayG0hYf9ZqsywL2Zvd5gwPg79i+K2JN1HYP5Ua08rCpHwP8plp ANeQ== X-Received: by 10.14.219.137 with SMTP id m9mr28974447eep.77.1395350763004; Thu, 20 Mar 2014 14:26:03 -0700 (PDT) Received: from sark.local (host151-4-dynamic.21-79-r.retail.telecomitalia.it. [79.21.4.151]) by mx.google.com with ESMTPSA id n5sm6941518eex.14.2014.03.20.14.26.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 20 Mar 2014 14:26:02 -0700 (PDT) From: Beniamino Galvani To: qemu-devel@nongnu.org Date: Thu, 20 Mar 2014 22:25:14 +0100 Message-Id: <1395350719-3778-3-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> References: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c00::22b Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Subject: [Qemu-devel] [PATCH v4 2/7] allwinner-a10-pic: fix behaviour of pending register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The pending register is read-only and the value returned upon a read reflects the state of irq input pins (interrupts are level triggered). This patch implements such behaviour. Signed-off-by: Beniamino Galvani Reviewed-by: Li Guang Reviewed-by: Peter Crosthwaite --- hw/intc/allwinner-a10-pic.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 00f3c11..0924d98 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level) if (level) { set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); + } else { + clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); } aw_a10_pic_update(s); } @@ -102,7 +104,11 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, s->nmi = value; break; case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: - s->irq_pending[index] &= ~value; + /* + * The register is read-only; nevertheless, Linux (including + * the version originally shipped by Allwinner) pretends to + * write to the register. Just ignore it. + */ break; case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: s->fiq_pending[index] &= ~value;