From patchwork Mon Mar 17 16:00:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 331071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2B5E22C00B7 for ; Tue, 18 Mar 2014 03:05:04 +1100 (EST) Received: from localhost ([::1]:58774 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPa29-0001jz-Sv for incoming@patchwork.ozlabs.org; Mon, 17 Mar 2014 12:05:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPZy7-0005NX-9H for qemu-devel@nongnu.org; Mon, 17 Mar 2014 12:00:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPZxz-0007gm-8Q for qemu-devel@nongnu.org; Mon, 17 Mar 2014 12:00:51 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46882) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPZxy-0007gB-QD; Mon, 17 Mar 2014 12:00:43 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WPZxx-0004vr-Ak; Mon, 17 Mar 2014 16:00:41 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Mar 2014 16:00:35 +0000 Message-Id: <1395072041-18911-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395072041-18911-1-git-send-email-peter.maydell@linaro.org> References: <1395072041-18911-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-trivial@nongnu.org, qemu-ppc@nongnu.org, patches@linaro.org Subject: [Qemu-devel] [PATCH v2 06/12] hw/usb/hcd-ohci.c: Avoid shifting left into sign bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add U suffix to avoid undefined behaviour. This is only strictly necessary for the 1<<31 cases, but we add it for the other constants in these groups for consistency. Signed-off-by: Peter Maydell --- hw/usb/hcd-ohci.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 3d35058b..93f186f 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -234,15 +234,15 @@ struct ohci_iso_td { #define OHCI_STATUS_OCR (1<<3) #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) -#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ -#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ -#define OHCI_INTR_SF (1<<2) /* Start of frame */ -#define OHCI_INTR_RD (1<<3) /* Resume detect */ -#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ -#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ -#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ -#define OHCI_INTR_OC (1<<30) /* Ownership change */ -#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ +#define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ +#define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ +#define OHCI_INTR_SF (1U<<2) /* Start of frame */ +#define OHCI_INTR_RD (1U<<3) /* Resume detect */ +#define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ +#define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ +#define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ +#define OHCI_INTR_OC (1U<<30) /* Ownership change */ +#define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ #define OHCI_HCCA_SIZE 0x100 #define OHCI_HCCA_MASK 0xffffff00 @@ -253,7 +253,7 @@ struct ohci_iso_td { #define OHCI_FMI_FSMPS 0xffff0000 #define OHCI_FMI_FIT 0x80000000 -#define OHCI_FR_RT (1<<31) +#define OHCI_FR_RT (1U<<31) #define OHCI_LS_THRESH 0x628 @@ -265,12 +265,12 @@ struct ohci_iso_td { #define OHCI_RHA_NOCP (1<<12) #define OHCI_RHA_POTPGT_MASK 0xff000000 -#define OHCI_RHS_LPS (1<<0) -#define OHCI_RHS_OCI (1<<1) -#define OHCI_RHS_DRWE (1<<15) -#define OHCI_RHS_LPSC (1<<16) -#define OHCI_RHS_OCIC (1<<17) -#define OHCI_RHS_CRWE (1<<31) +#define OHCI_RHS_LPS (1U<<0) +#define OHCI_RHS_OCI (1U<<1) +#define OHCI_RHS_DRWE (1U<<15) +#define OHCI_RHS_LPSC (1U<<16) +#define OHCI_RHS_OCIC (1U<<17) +#define OHCI_RHS_CRWE (1U<<31) #define OHCI_PORT_CCS (1<<0) #define OHCI_PORT_PES (1<<1)