From patchwork Sat Mar 15 18:31:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 330668 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7E65C2C00A7 for ; Sun, 16 Mar 2014 05:31:59 +1100 (EST) Received: from localhost ([::1]:50845 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOtNE-00089M-Bp for incoming@patchwork.ozlabs.org; Sat, 15 Mar 2014 14:31:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45682) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOtMz-00085t-EH for qemu-devel@nongnu.org; Sat, 15 Mar 2014 14:31:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOtMy-0004fA-KB for qemu-devel@nongnu.org; Sat, 15 Mar 2014 14:31:41 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46870) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOtMy-0004dm-DR for qemu-devel@nongnu.org; Sat, 15 Mar 2014 14:31:40 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1WOtMp-0004JL-Pa; Sat, 15 Mar 2014 18:31:31 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Sat, 15 Mar 2014 18:31:31 +0000 Message-Id: <1394908291-16546-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Laurent Desnogues , Alistair Francis , patches@linaro.org Subject: [Qemu-devel] [PATCH] target-arm: Add ARM_CP_IO notation to PMCR reginfo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Now that the PMCR writefn makes timer accesses, its reginfo needs the ARM_CP_IO flag, so that icount mode works correctly. (Fixes the bug accidentally introduced in commit 7c2cb42b). Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target-arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index aa5f22d..e895879 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1983,6 +1983,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo pmcr = { .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000, + .type = ARM_CP_IO, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), .accessfn = pmreg_access, .writefn = pmcr_write, .raw_writefn = raw_write,