From patchwork Sat Mar 15 13:01:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 330647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6841D2C00BA for ; Sun, 16 Mar 2014 00:03:14 +1100 (EST) Received: from localhost ([::1]:50000 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoF6-00052A-0E for incoming@patchwork.ozlabs.org; Sat, 15 Mar 2014 09:03:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoER-0004ZL-Hn for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOoEJ-0003aK-1G for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:31 -0400 Received: from mail-ee0-x236.google.com ([2a00:1450:4013:c00::236]:40339) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoEI-0003a9-Ql for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:22 -0400 Received: by mail-ee0-f54.google.com with SMTP id d49so2389051eek.27 for ; Sat, 15 Mar 2014 06:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mh8ayGTBV6xxcbA7qImaDG08Wy9Dh6OgbL1nss7GiaY=; b=XYkMmVgNvXD4vf8Pb6EUAMoQA7Mzd1A9RYgwYpUQTt0Cnrdgonfo5Bd+VmOH/PWixt eeKQ+1VJjzd+qHDZWjsJ+TjMUcGMwJhtsrwbIWLNzlDCuFulQqoHR6OwVtEjsBKf98+P 4APuqtZDWBYx+JBN6gixY3xGS2Mwyho20nMfBpnhVaK2MnnGk6egaB9yNYTiZEAFbkGk J+41fuuuv4sKri1XXIH3WgY89dpBJtXozMlvq9k1me8wKQO0CUXVqKU5Pl+iQEe/mmzr G381YZZGxf2NW17mN0Max7bBmjfC3Ogs+c0wsuq72kCQMP37A7PzxgXfBlpBnMvXBmao MK0A== X-Received: by 10.15.31.137 with SMTP id y9mr13938472eeu.12.1394888541950; Sat, 15 Mar 2014 06:02:21 -0700 (PDT) Received: from sark.local (host151-4-dynamic.21-79-r.retail.telecomitalia.it. [79.21.4.151]) by mx.google.com with ESMTPSA id j41sm24566424eeg.10.2014.03.15.06.02.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Mar 2014 06:02:21 -0700 (PDT) From: Beniamino Galvani To: qemu-devel@nongnu.org Date: Sat, 15 Mar 2014 14:01:30 +0100 Message-Id: <1394888493-20487-5-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> References: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c00::236 Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Subject: [Qemu-devel] [PATCH v3 4/7] allwinner-a10-pit: use level triggered interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite --- hw/timer/allwinner-a10-pit.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 696b7d9..f8c9236 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -19,6 +19,15 @@ #include "sysemu/sysemu.h" #include "hw/timer/allwinner-a10-pit.h" +static void a10_pit_update_irq(AwA10PITState *s) +{ + int i; + + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + qemu_set_irq(s->irq[i], s->irq_status & s->irq_enable & (1 << i)); + } +} + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -74,9 +83,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -203,7 +214,7 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i]); s->control[i] &= ~AW_A10_PIT_TIMER_EN; } - qemu_irq_pulse(s->irq[i]); + a10_pit_update_irq(s); } }