From patchwork Sat Mar 15 13:01:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 330646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A1BF92C00BC for ; Sun, 16 Mar 2014 00:02:55 +1100 (EST) Received: from localhost ([::1]:49999 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoEn-0004WO-5i for incoming@patchwork.ozlabs.org; Sat, 15 Mar 2014 09:02:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoEJ-0004Jf-8k for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOoED-0003ZS-Ef for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:23 -0400 Received: from mail-ee0-x230.google.com ([2a00:1450:4013:c00::230]:45249) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoED-0003ZC-7L for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:17 -0400 Received: by mail-ee0-f48.google.com with SMTP id b57so1687009eek.7 for ; Sat, 15 Mar 2014 06:02:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ITMgL4IC+e0n6BEoA+vBK3pi63klHo7Bz2An3wLvOIQ=; b=ajc/g5fy1A3iDHGWGpw0RH661HvEIwUdofvQ41lnV6dMEooJy8uSQUhxYXYz1unt+2 hX8kdGjFIG1iV5KmLd+ZLUno05waJ5rtnHHoScDD6B0fQkA5Q6mgi0cc/0Gvz9VqPpDt R6bN7H0S+raJeWZheUOvlPMGK1WmEw67vAc4DpgJPx6aHzyyFsgGiWaTknVe2F3b6EDx ArE0pI0ZREZgpIDAzOW4W/GKU7/c3JRA+5oQJOMJIKkVW7R6rz7z0dLGPi5F3GQT+sHk gZq2uioQd6Kb13MFDm98qrPXJPpGVudE7OltWvJ58Wd8tMls2bt+54wHt6+kRiJ8ftqJ Wx7w== X-Received: by 10.14.193.201 with SMTP id k49mr13969122een.50.1394888536365; Sat, 15 Mar 2014 06:02:16 -0700 (PDT) Received: from sark.local (host151-4-dynamic.21-79-r.retail.telecomitalia.it. [79.21.4.151]) by mx.google.com with ESMTPSA id j41sm24566424eeg.10.2014.03.15.06.02.14 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Mar 2014 06:02:15 -0700 (PDT) From: Beniamino Galvani To: qemu-devel@nongnu.org Date: Sat, 15 Mar 2014 14:01:27 +0100 Message-Id: <1394888493-20487-2-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> References: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c00::230 Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Subject: [Qemu-devel] [PATCH v3 1/7] allwinner-a10-pic: set vector address when an interrupt is pending X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements proper updating of the vector register which should hold, according to the A10 user manual, the vector address for the interrupt currently active on the CPU IRQ input. Interrupt priority is not implemented at the moment and thus the first pending interrupt is returned. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite Reviewed-by: Li Guang --- hw/intc/allwinner-a10-pic.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 407d563..00f3c11 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -23,11 +23,20 @@ static void aw_a10_pic_update(AwA10PICState *s) { uint8_t i; - int irq = 0, fiq = 0; + int irq = 0, fiq = 0, pending; + + s->vector = 0; for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { irq |= s->irq_pending[i] & ~s->mask[i]; fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; + + if (!s->vector) { + pending = ffs(s->irq_pending[i] & ~s->mask[i]); + if (pending) { + s->vector = (i * 32 + pending - 1) * 4; + } + } } qemu_set_irq(s->parent_irq, !!irq); @@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, uint8_t index = (offset & 0xc) / 4; switch (offset) { - case AW_A10_PIC_VECTOR: - s->vector = value & ~0x3; - break; case AW_A10_PIC_BASE_ADDR: s->base_addr = value & ~0x3; case AW_A10_PIC_PROTECT: