From patchwork Fri Mar 14 12:47:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Hogan X-Patchwork-Id: 330296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C840C2C00B5 for ; Fri, 14 Mar 2014 23:51:35 +1100 (EST) Received: from localhost ([::1]:44525 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WORaH-0008TZ-CS for incoming@patchwork.ozlabs.org; Fri, 14 Mar 2014 08:51:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55975) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WORXL-0003bf-64 for qemu-devel@nongnu.org; Fri, 14 Mar 2014 08:48:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WORXH-0006Bn-3F for qemu-devel@nongnu.org; Fri, 14 Mar 2014 08:48:31 -0400 Received: from mailapp01.imgtec.com ([195.89.28.115]:48719) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WORXG-0006BX-Q9 for qemu-devel@nongnu.org; Fri, 14 Mar 2014 08:48:27 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id E749988B8A3AE; Fri, 14 Mar 2014 12:48:21 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 14 Mar 2014 12:48:24 +0000 Received: from jhogan-linux.le.imgtec.org (192.168.154.65) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 14 Mar 2014 12:48:23 +0000 From: James Hogan To: Date: Fri, 14 Mar 2014 12:47:59 +0000 Message-ID: <1394801281-18997-9-git-send-email-james.hogan@imgtec.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1394801281-18997-1-git-send-email-james.hogan@imgtec.com> References: <1394801281-18997-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.65] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.89.28.115 Cc: Peter Maydell , James Hogan , kvm@vger.kernel.org, Gleb Natapov , Sanjay Lal , Paolo Bonzini , Aurelien Jarno Subject: [Qemu-devel] [PATCH v4 08/10] hw/mips: malta: Add KVM support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In KVM mode the bootrom is loaded and executed from the last 1MB of DRAM. Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for SMP Guests" by Sanjay Lal . Signed-off-by: James Hogan Reviewed-by: Aurelien Jarno Cc: Peter Maydell Cc: Sanjay Lal --- Changes in v3: - Remove unnecessary includes, especially linux/kvm.h which isn't a good idea on non-Linux (Peter Maydell). Changes in v2: - Removal of cps / GIC / SMP support - Minimal bootloader modified to execute safely from RAM - Remove "Writing bootloader to final 1MB of RAM" printf --- hw/mips/mips_malta.c | 82 ++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 60 insertions(+), 22 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index ac5ec44..90b20d6 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -51,6 +51,7 @@ #include "sysemu/qtest.h" #include "qemu/error-report.h" #include "hw/empty_slot.h" +#include "sysemu/kvm.h" //#define DEBUG_BOARD_INIT @@ -603,29 +604,31 @@ static void network_init(PCIBus *pci_bus) */ static void write_bootloader (CPUMIPSState *env, uint8_t *base, - int64_t kernel_entry) + int64_t run_addr, int64_t kernel_entry) { uint32_t *p; /* Small bootloader */ p = (uint32_t *)base; - stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */ + + stl_raw(p++, 0x08000000 | /* j 0x1fc00580 */ + ((run_addr + 0x580) & 0x0fffffff) >> 2); stl_raw(p++, 0x00000000); /* nop */ /* YAMON service vector */ - stl_raw(base + 0x500, 0xbfc00580); /* start: */ - stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */ - stl_raw(base + 0x520, 0xbfc00580); /* start: */ - stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */ - stl_raw(base + 0x534, 0xbfc00808); /* print: */ - stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */ - stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */ - stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */ - stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */ - stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */ - stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */ - stl_raw(base + 0x550, 0xbfc00800); /* getchar: */ - stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */ + stl_raw(base + 0x500, run_addr + 0x0580); /* start: */ + stl_raw(base + 0x504, run_addr + 0x083c); /* print_count: */ + stl_raw(base + 0x520, run_addr + 0x0580); /* start: */ + stl_raw(base + 0x52c, run_addr + 0x0800); /* flush_cache: */ + stl_raw(base + 0x534, run_addr + 0x0808); /* print: */ + stl_raw(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */ + stl_raw(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */ + stl_raw(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */ + stl_raw(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */ + stl_raw(base + 0x548, run_addr + 0x0800); /* reg_esr: */ + stl_raw(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */ + stl_raw(base + 0x550, run_addr + 0x0800); /* getchar: */ + stl_raw(base + 0x554, run_addr + 0x0800); /* syscon_read: */ /* Second part of the bootloader */ @@ -701,7 +704,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, p = (uint32_t *) (base + 0x800); stl_raw(p++, 0x03e00008); /* jr ra */ stl_raw(p++, 0x24020000); /* li v0,0 */ - /* 808 YAMON print */ + /* 808 YAMON print */ stl_raw(p++, 0x03e06821); /* move t5,ra */ stl_raw(p++, 0x00805821); /* move t3,a0 */ stl_raw(p++, 0x00a05021); /* move t2,a1 */ @@ -774,6 +777,9 @@ static int64_t load_kernel (void) uint32_t *prom_buf; long prom_size; int prom_index = 0; + uint64_t (*xlate_to_phys) (void *opaque, uint64_t addr); + uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr); + #ifdef TARGET_WORDS_BIGENDIAN big_endian = 1; @@ -781,7 +787,15 @@ static int64_t load_kernel (void) big_endian = 0; #endif - if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL, + if (kvm_enabled()) { + xlate_to_phys = cpu_mips_kvm_um_kseg0_to_phys; + xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0; + } else { + xlate_to_phys = cpu_mips_kseg0_to_phys; + xlate_to_kseg0 = cpu_mips_phys_to_kseg0; + } + + if (load_elf(loaderparams.kernel_filename, xlate_to_phys, NULL, (uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high, big_endian, ELF_MACHINE, 1) < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", @@ -820,7 +834,7 @@ static int64_t load_kernel (void) prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename); if (initrd_size > 0) { prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s", - cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size, + xlate_to_kseg0(NULL, initrd_offset), initrd_size, loaderparams.kernel_cmdline); } else { prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline); @@ -829,12 +843,13 @@ static int64_t load_kernel (void) prom_set(prom_buf, prom_index++, "memsize"); prom_set(prom_buf, prom_index++, "%i", MIN(loaderparams.ram_size, 256 << 20)); + prom_set(prom_buf, prom_index++, "modetty0"); prom_set(prom_buf, prom_index++, "38400n8r"); prom_set(prom_buf, prom_index++, NULL); rom_add_blob_fixed("prom", prom_buf, prom_size, - cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); + xlate_to_phys(NULL, ENVP_ADDR)); return kernel_entry; } @@ -863,6 +878,11 @@ static void main_cpu_reset(void *opaque) } malta_mips_config(cpu); + + if (kvm_enabled()) { + /* Start running from the bootloader we wrote to end of RAM */ + env->active_tc.PC = 0x40000000 + loaderparams.ram_size; + } } static void cpu_request_exit(void *opaque, int irq, int level) @@ -878,6 +898,7 @@ static void mips_malta_init(QEMUMachineInitArgs *args) { ram_addr_t ram_size = args->ram_size; + ram_addr_t ram_low_size; const char *cpu_model = args->cpu_model; const char *kernel_filename = args->kernel_filename; const char *kernel_cmdline = args->kernel_cmdline; @@ -892,7 +913,7 @@ void mips_malta_init(QEMUMachineInitArgs *args) target_long bios_size = FLASH_SIZE; const size_t smbus_eeprom_size = 8 * 256; uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); - int64_t kernel_entry; + int64_t kernel_entry, bootloader_run_addr; PCIBus *pci_bus; ISABus *isa_bus; MIPSCPU *cpu; @@ -1011,13 +1032,30 @@ void mips_malta_init(QEMUMachineInitArgs *args) bios = pflash_cfi01_get_memory(fl); fl_idx++; if (kernel_filename) { + ram_low_size = MIN(ram_size, 256 << 20); + /* For KVM T&E we reserve 1MB of RAM for running bootloader */ + if (kvm_enabled()) { + ram_low_size -= 0x100000; + bootloader_run_addr = 0x40000000 + ram_low_size; + } else { + bootloader_run_addr = 0xbfc00000; + } + /* Write a small bootloader to the flash location. */ - loaderparams.ram_size = MIN(ram_size, 256 << 20); + loaderparams.ram_size = ram_low_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(); - write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); + + write_bootloader(env, memory_region_get_ram_ptr(bios), + bootloader_run_addr, kernel_entry); + if (kvm_enabled()) { + /* Write the bootloader code @ the end of RAM, 1MB reserved */ + write_bootloader(env, memory_region_get_ram_ptr(ram_low_preio) + + ram_low_size, + bootloader_run_addr, kernel_entry); + } } else { /* Load firmware from flash. */ if (!dinfo) {