From patchwork Wed Mar 12 16:40:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gabriel L. Somlo" X-Patchwork-Id: 329555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6A1FF2C00B8 for ; Thu, 13 Mar 2014 03:46:28 +1100 (EST) Received: from localhost ([::1]:33543 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNmIU-0007Jb-9k for incoming@patchwork.ozlabs.org; Wed, 12 Mar 2014 12:46:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNmFt-0003FZ-Tp for qemu-devel@nongnu.org; Wed, 12 Mar 2014 12:43:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WNmFm-0008TY-G8 for qemu-devel@nongnu.org; Wed, 12 Mar 2014 12:43:45 -0400 Received: from mail-qc0-x22e.google.com ([2607:f8b0:400d:c01::22e]:59939) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WNmFm-0008TR-A6 for qemu-devel@nongnu.org; Wed, 12 Mar 2014 12:43:38 -0400 Received: by mail-qc0-f174.google.com with SMTP id x13so11670159qcv.33 for ; Wed, 12 Mar 2014 09:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jTu/B5B/9jCpXXVrDgWFXdoGaD1k9Z01XRNmDqZQbfA=; b=u53x0xHLylOOp4WwZoncFtDfoBQ4EVZTdpH8X0o9AKaw7fAUD4KU5LBZLaM7BvCdst NIHzGPUKg+p7ueBn+6QxnqurdjNjffkqjvgoMhm4FEDYOn7Yg134QXrRyv9kHRD4/jyJ LqF+ytw7lu3jtodb1XNDqpzvvTeyaqxYHi9TDu0XNA/eBYSwINnYEz7eLd7wl1DO8sN0 WQC5lKqtKbwf10gL9wtnGAjPCkC8ARy+RaPyGr+yD1GfXE/UlFQnv1zHH+GydbMCDwaU DIZpza2b5jhuU+qSSUr0NHhU09TamDYO21xueWpKT5KMRVtWXeu6DvLzefzSbER6x/RQ 7v/Q== X-Received: by 10.140.94.68 with SMTP id f62mr47494273qge.64.1394642617856; Wed, 12 Mar 2014 09:43:37 -0700 (PDT) Received: from ERROL.ini.cmu.edu (ERROL.INI.CMU.EDU. [128.2.16.43]) by mx.google.com with ESMTPSA id u15sm35106301qge.2.2014.03.12.09.43.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Mar 2014 09:43:37 -0700 (PDT) From: "Gabriel L. Somlo" To: qemu-devel@nongnu.org Date: Wed, 12 Mar 2014 12:40:07 -0400 Message-Id: <1394642412-29317-9-git-send-email-somlo@cmu.edu> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1394642412-29317-1-git-send-email-somlo@cmu.edu> References: <1394612454.17393.16.camel@nilsson.home.kraxel.org> <1394642412-29317-1-git-send-email-somlo@cmu.edu> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::22e Cc: agraf@suse.de, gsomlo@gmail.com, armbru@redhat.com, alex.williamson@redhat.com, kevin@koconnor.net, kraxel@redhat.com, lersek@redhat.com Subject: [Qemu-devel] [v3 PATCH 08/13] SMBIOS: Build full type 4 tables X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Gabriel L. Somlo" Build full smbios type 4 (processor information) tables, and make them available to the bios via fw_cfg. For initial compatibility with SeaBIOS, use "Bochs" as the default manufacturer string, and leave version unset. Signed-off-by: Gabriel Somlo --- hw/i386/pc.c | 3 ++ hw/i386/smbios.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/smbios.h | 1 + 3 files changed, 100 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e715a33..9c4623e 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1011,6 +1011,9 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, APIC_DEFAULT_ADDRESS, 0x1000); } + + /* tell smbios about cpuid version and features */ + smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); } /* pci-info ROM file. Little endian format */ diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c index 47f7b0d..fc8b3ef 100644 --- a/hw/i386/smbios.c +++ b/hw/i386/smbios.c @@ -42,6 +42,7 @@ static size_t smbios_entries_len; static int smbios_type4_count = 0; static bool smbios_immutable; static bool smbios_have_defaults; +static uint32_t smbios_cpuid_version, smbios_cpuid_features; /* for type 4 */ static DECLARE_BITMAP(have_binfile_bitmap, SMBIOS_MAX_TYPE+1); static DECLARE_BITMAP(have_fields_bitmap, SMBIOS_MAX_TYPE+1); @@ -65,6 +66,10 @@ static struct { const char *manufacturer, *version, *serial, *asset; } type3; +static struct { + const char *sock_pfx, *manufacturer, *version, *serial, *asset, *part; +} type4; + static QemuOptsList qemu_smbios_opts = { .name = "smbios", .head = QTAILQ_HEAD_INITIALIZER(qemu_smbios_opts.head), @@ -206,6 +211,39 @@ static const QemuOptDesc qemu_smbios_type3_opts[] = { { /* end of list */ } }; +static const QemuOptDesc qemu_smbios_type4_opts[] = { + { + .name = "type", + .type = QEMU_OPT_NUMBER, + .help = "SMBIOS element type", + },{ + .name = "sock_pfx", + .type = QEMU_OPT_STRING, + .help = "socket designation string prefix", + },{ + .name = "manufacturer", + .type = QEMU_OPT_STRING, + .help = "manufacturer name", + },{ + .name = "version", + .type = QEMU_OPT_STRING, + .help = "version number", + },{ + .name = "serial", + .type = QEMU_OPT_STRING, + .help = "serial number", + },{ + .name = "asset", + .type = QEMU_OPT_STRING, + .help = "asset tag number", + },{ + .name = "part", + .type = QEMU_OPT_STRING, + .help = "part number", + }, + { /* end of list */ } +}; + static void smbios_register_config(void) { qemu_add_opts(&qemu_smbios_opts); @@ -400,11 +438,45 @@ static void smbios_build_type_3_table(void) SMBIOS_BUILD_TABLE_POST; } +static void smbios_build_type_4_table(unsigned instance) +{ + char sock_str[128]; + + SMBIOS_BUILD_TABLE_PRE(4, 0x400 + instance, true); /* required */ + + snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance); + SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str); + t->processor_type = 0x03; /* CPU */ + t->processor_family = 0x01; /* Other */ + SMBIOS_TABLE_SET_STR(4, processor_manufacturer_str, type4.manufacturer); + t->processor_id[0] = smbios_cpuid_version; + t->processor_id[1] = smbios_cpuid_features; + SMBIOS_TABLE_SET_STR(4, processor_version_str, type4.version); + t->voltage = 0; + t->external_clock = 0; + t->max_speed = 2000; /* hardcoded in SeaBIOS (use 0/Unknown instead ?) */ + t->current_speed = 2000; /* hardcoded in SeaBIOS (use 0/Unknown ?) */ + t->status = 0x41; /* Socket populated, CPU enabled */ + t->processor_upgrade = 0x01; /* Other */ + t->l1_cache_handle = 0xFFFF; /* N/A */ + t->l2_cache_handle = 0xFFFF; /* N/A */ + t->l3_cache_handle = 0xFFFF; /* N/A */ + + SMBIOS_BUILD_TABLE_POST; + smbios_type4_count++; +} + #define SMBIOS_SET_DEFAULT(field, value) \ if (!field) { \ field = value; \ } +void smbios_set_cpuid(uint32_t version, uint32_t features) +{ + smbios_cpuid_version = version; + smbios_cpuid_features = features; +} + void smbios_set_defaults(const char *manufacturer, const char *product, const char *version) { @@ -423,15 +495,26 @@ void smbios_set_defaults(const char *manufacturer, /* not set in SeaBIOS SMBIOS_SET_DEFAULT(type3.version, version); */ + SMBIOS_SET_DEFAULT(type4.sock_pfx, "CPU"); + SMBIOS_SET_DEFAULT(type4.manufacturer, manufacturer_compat); + /* not set in SeaBIOS + SMBIOS_SET_DEFAULT(type4.version, version); + */ } uint8_t *smbios_get_table(size_t *length) { + unsigned i; + if (!smbios_immutable) { smbios_build_type_0_table(); smbios_build_type_1_table(); smbios_build_type_2_table(); smbios_build_type_3_table(); + for (i = 0; i < smp_cpus; i++) { + /* count CPUs starting with 1, to minimize diff vs. SeaBIOS */ + smbios_build_type_4_table(i + 1); + } smbios_validate_table(); smbios_immutable = true; } @@ -589,6 +672,19 @@ void smbios_entry_add(QemuOpts *opts) save_opt(&type3.serial, opts, "serial"); save_opt(&type3.asset, opts, "asset"); return; + case 4: + qemu_opts_validate(opts, qemu_smbios_type4_opts, &local_err); + if (local_err) { + error_report("%s", error_get_pretty(local_err)); + exit(1); + } + save_opt(&type4.sock_pfx, opts, "sock_pfx"); + save_opt(&type4.manufacturer, opts, "manufacturer"); + save_opt(&type4.version, opts, "version"); + save_opt(&type4.serial, opts, "serial"); + save_opt(&type4.asset, opts, "asset"); + save_opt(&type4.part, opts, "part"); + return; default: error_report("Don't know how to build fields for SMBIOS type %ld", type); diff --git a/include/hw/i386/smbios.h b/include/hw/i386/smbios.h index 2642e1a..af5ee01 100644 --- a/include/hw/i386/smbios.h +++ b/include/hw/i386/smbios.h @@ -18,6 +18,7 @@ #define SMBIOS_MAX_TYPE 127 void smbios_entry_add(QemuOpts *opts); +void smbios_set_cpuid(uint32_t version, uint32_t features); void smbios_set_defaults(const char *manufacturer, const char *product, const char *version); uint8_t *smbios_get_table(size_t *length);