From patchwork Thu Mar 6 23:33:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 327665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5B5822C0334 for ; Fri, 7 Mar 2014 11:38:52 +1100 (EST) Received: from localhost ([::1]:33684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLioM-000724-7c for incoming@patchwork.ozlabs.org; Thu, 06 Mar 2014 19:38:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLhoT-0001Ab-Q0 for qemu-devel@nongnu.org; Thu, 06 Mar 2014 18:35:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WLhny-0003Ns-9N for qemu-devel@nongnu.org; Thu, 06 Mar 2014 18:34:53 -0500 Received: from cantor2.suse.de ([195.135.220.15]:55855 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WLhny-0003Eu-30; Thu, 06 Mar 2014 18:34:22 -0500 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id D381DAD20; Thu, 6 Mar 2014 23:34:21 +0000 (UTC) From: Alexander Graf To: qemu-devel@nongnu.org Date: Fri, 7 Mar 2014 00:33:36 +0100 Message-Id: <1394148857-19607-90-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1394148857-19607-1-git-send-email-agraf@suse.de> References: <1394148857-19607-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , Tom Musta , blauwirbel@gmail.com, qemu-ppc@nongnu.org, aliguori@amazon.com, aurelien@aurel32.net Subject: [Qemu-devel] [PULL 089/130] target-ppc: Add Load Quadword and Reserve X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Tom Musta This patch adds the Load Quadword and Reserve (lqarx) instruction, which is new in Power ISA 2.07. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 1 + target-ppc/translate.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 365627b..7cf7255 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -926,6 +926,7 @@ struct CPUPPCState { target_ulong reserve_addr; /* Reservation value */ target_ulong reserve_val; + target_ulong reserve_val2; /* Reservation store address */ target_ulong reserve_ea; /* Reserved store source register and size */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 72eff90..13c9802 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3359,6 +3359,42 @@ STCX(stwcx_, 4); /* ldarx */ LARX(ldarx, 8, ld64); +/* lqarx */ +static void gen_lqarx(DisasContext *ctx) +{ + TCGv EA; + int rd = rD(ctx->opcode); + TCGv gpr1, gpr2; + + if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || + (rd == rB(ctx->opcode)))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return; + } + + gen_set_access_type(ctx, ACCESS_RES); + EA = tcg_temp_local_new(); + gen_addr_reg_index(ctx, EA); + gen_check_align(ctx, EA, 15); + if (unlikely(ctx->le_mode)) { + gpr1 = cpu_gpr[rd+1]; + gpr2 = cpu_gpr[rd]; + } else { + gpr1 = cpu_gpr[rd]; + gpr2 = cpu_gpr[rd+1]; + } + gen_qemu_ld64(ctx, gpr1, EA); + tcg_gen_mov_tl(cpu_reserve, EA); + + gen_addr_add(ctx, EA, EA, 8); + gen_qemu_ld64(ctx, gpr2, EA); + + tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); + + tcg_temp_free(EA); +} + /* stdcx. */ STCX(stdcx_, 8); #endif /* defined(TARGET_PPC64) */ @@ -9623,6 +9659,7 @@ GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), +GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), #endif GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),