From patchwork Sun Mar 2 14:06:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 325579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0718C2C00C2 for ; Mon, 3 Mar 2014 01:08:10 +1100 (EST) Received: from localhost ([::1]:35580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK73n-000062-98 for incoming@patchwork.ozlabs.org; Sun, 02 Mar 2014 09:08:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK73D-0008IQ-EO for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WK735-0003T3-0T for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:31 -0500 Received: from mail-ea0-x235.google.com ([2a00:1450:4013:c01::235]:36002) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK734-0003Sv-QU for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:22 -0500 Received: by mail-ea0-f181.google.com with SMTP id k10so3798712eaj.40 for ; Sun, 02 Mar 2014 06:07:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BZPC93HFyFieHZ37l6vrX1RsnoXqyRPgH+CHLFFG3W4=; b=BKHZoFz+Rx4ljyKUg4boEawc4QkVPPX6UxWcUEEYIJQ7v/b+HLdSTs1FQOkCbf4ZCN sxlyfpk3I9Ifd8wFKCh0gaAmatX7EUQoJLprljR2/WHPIQtz6GR/vSfIyC5h4m0/Z9jn rx88J6kSSSaGIQFzS1S1CFlhKrwYj1HBXjjBo7ar8ENkIljr8VRfiSXJ/JEGV5TLrjQG GsieKX3yKb0KAq6w8XGIgALySaHpHp2pOArsjebO8zt5TSoHPtxv53+wl49cE1Q1oR45 Ouq6WZOuL7jEgqHClhYrRs6V1f4mB+J4ES8gtGeWQ9Xch+GEgR3di90F6tgosEbAWS81 AF9Q== X-Received: by 10.14.88.131 with SMTP id a3mr33849789eef.64.1393769242188; Sun, 02 Mar 2014 06:07:22 -0800 (PST) Received: from sark.local (host199-98-dynamic.25-79-r.retail.telecomitalia.it. [79.25.98.199]) by mx.google.com with ESMTPSA id m1sm36986447een.7.2014.03.02.06.07.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Mar 2014 06:07:21 -0800 (PST) From: Beniamino Galvani To: qemu-devel@nongnu.org Date: Sun, 2 Mar 2014 15:06:39 +0100 Message-Id: <1393769202-4551-6-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> References: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c01::235 Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Subject: [Qemu-devel] [PATCH v2 5/7] allwinner-a10-pit: implement prescaler and source selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This implements the prescaler and source fields of the timer control register as described in the A10 user manual. Signed-off-by: Beniamino Galvani --- hw/timer/allwinner-a10-pit.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 4723b25..f2f2567 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -79,6 +79,23 @@ static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) return 0; } +static void a10_pit_set_freq(AwA10PITState *s, int index) +{ + uint32_t prescaler, source; + uint32_t source_freqs[] = {32768, 24000000}; + + prescaler = 1 << extract32(s->control[index], 4, 3); + source = extract32(s->control[index], 2, 2); + + if (source > 1) { + qemu_log_mask(LOG_UNIMP, "%s: unimplemented clock source %d", + __func__, source); + source = 0; + } + + ptimer_set_freq(s->timer[index], source_freqs[source] / prescaler); +} + static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -101,6 +118,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset & 0x0f) { case AW_A10_PIT_TIMER_CONTROL: s->control[index] = value; + a10_pit_set_freq(s, index); if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { ptimer_set_count(s->timer[index], s->interval[index]); } @@ -244,7 +262,6 @@ static void a10_pit_init(Object *obj) tc->index = i; bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); s->timer[i] = ptimer_init(bh[i]); - ptimer_set_freq(s->timer[i], 240000); } }