From patchwork Sun Mar 2 14:06:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 325583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2C7932C00C2 for ; Mon, 3 Mar 2014 01:10:38 +1100 (EST) Received: from localhost ([::1]:35602 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK76B-0004kS-Gn for incoming@patchwork.ozlabs.org; Sun, 02 Mar 2014 09:10:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56013) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK739-0008F0-Jt for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WK730-0003S3-UA for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:27 -0500 Received: from mail-ea0-x236.google.com ([2a00:1450:4013:c01::236]:47620) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WK730-0003RJ-Oa for qemu-devel@nongnu.org; Sun, 02 Mar 2014 09:07:18 -0500 Received: by mail-ea0-f182.google.com with SMTP id b10so2909278eae.13 for ; Sun, 02 Mar 2014 06:07:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k2CILLjkwOFD7jgrddVt+eaCgh4CfvgQFH5hWYus6Vk=; b=jkdMLtUZT1FFU+84vUGOlHRTjOu4jtleT2bXd+VxE9KSozSbqZgB0BKuW6viW1GGa1 wPv7pL0Vrdpa0wbJxust7pzkVaSwaJePE1rGxJua8Gm+ZoJfYge9X+HMd8JrVD5Mxrfp RgOlG3Vkyi3HSBRYikoO9/t6prA6XsiMHHh2ucWY4kB6//zIQq+8Jisc+OCRMz13yMZn z44Q39ieU0xHMeGQVpJ3JJhRbn4DjyIUzV2OpKGMBXqXueyNe0zd7dfS3/itFxojlzx5 +52eLAPSJTppA8nxaLjbiQi7nd9GzkgsqBodduYvMKSW7fwx4fMPuw/WLv6Xnm2/VWSs Seog== X-Received: by 10.14.203.197 with SMTP id f45mr5140277eeo.90.1393769238130; Sun, 02 Mar 2014 06:07:18 -0800 (PST) Received: from sark.local (host199-98-dynamic.25-79-r.retail.telecomitalia.it. [79.25.98.199]) by mx.google.com with ESMTPSA id m1sm36986447een.7.2014.03.02.06.07.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Mar 2014 06:07:17 -0800 (PST) From: Beniamino Galvani To: qemu-devel@nongnu.org Date: Sun, 2 Mar 2014 15:06:37 +0100 Message-Id: <1393769202-4551-4-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> References: <1393769202-4551-1-git-send-email-b.galvani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4013:c01::236 Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Subject: [Qemu-devel] [PATCH v2 3/7] allwinner-a10-pit: avoid generation of spurious interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The model was generating interrupts for all enabled timers after the expiration of one of them. Avoid this by passing to the timer callback function a structure containing the index of the expired timer. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite --- hw/timer/allwinner-a10-pit.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index b27fce8..3e1c183 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -19,6 +19,11 @@ #include "sysemu/sysemu.h" #include "hw/timer/allwinner-a10-pit.h" +typedef struct TimerContext { + AwA10PITState *state; + int index; +} TimerContext; + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -193,18 +198,17 @@ static void a10_pit_reset(DeviceState *dev) static void a10_pit_timer_cb(void *opaque) { - AwA10PITState *s = AW_A10_PIT(opaque); - uint8_t i; + TimerContext *tc = opaque; + AwA10PITState *s = tc->state; + uint8_t i = tc->index; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - if (s->control[i] & AW_A10_PIT_TIMER_EN) { - s->irq_status |= 1 << i; - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { - ptimer_stop(s->timer[i]); - s->control[i] &= ~AW_A10_PIT_TIMER_EN; - } - qemu_irq_pulse(s->irq[i]); + if (s->control[i] & AW_A10_PIT_TIMER_EN) { + s->irq_status |= 1 << i; + if (s->control[i] & AW_A10_PIT_TIMER_MODE) { + ptimer_stop(s->timer[i]); + s->control[i] &= ~AW_A10_PIT_TIMER_EN; } + qemu_irq_pulse(s->irq[i]); } } @@ -213,6 +217,7 @@ static void a10_pit_init(Object *obj) AwA10PITState *s = AW_A10_PIT(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); QEMUBH * bh[AW_A10_PIT_TIMER_NR]; + TimerContext *tc; uint8_t i; for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { @@ -223,7 +228,10 @@ static void a10_pit_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - bh[i] = qemu_bh_new(a10_pit_timer_cb, s); + tc = g_malloc(sizeof(TimerContext)); + tc->state = s; + tc->index = i; + bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); s->timer[i] = ptimer_init(bh[i]); ptimer_set_freq(s->timer[i], 240000); }