From patchwork Tue Jan 28 11:22:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 314692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 564572C0082 for ; Tue, 28 Jan 2014 22:24:12 +1100 (EST) Received: from localhost ([::1]:36657 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W86m2-00068x-0k for incoming@patchwork.ozlabs.org; Tue, 28 Jan 2014 06:24:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W86ks-0003qi-C9 for qemu-devel@nongnu.org; Tue, 28 Jan 2014 06:23:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W86kl-0000c9-Am for qemu-devel@nongnu.org; Tue, 28 Jan 2014 06:22:58 -0500 Received: from mail-la0-f45.google.com ([209.85.215.45]:65076) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W86kl-0000bu-3c for qemu-devel@nongnu.org; Tue, 28 Jan 2014 06:22:51 -0500 Received: by mail-la0-f45.google.com with SMTP id b8so203035lan.4 for ; Tue, 28 Jan 2014 03:22:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mtC5vG01XFZDOLxVOewr4zt6fp1T0b2/eL8YiGsS0ck=; b=jw3Aw2E24FkVc0q56XqHvim/GYw8Hb+d5AgSUqRKHCGhPSWU1rejuNEdedtKHLDJM5 78k23s+9GWQ5Qq1njMWETlY5p8WxPkiL9Tf60KKNH4WSxvcBenfXGptGAbjm8+KRwbKC 7XZUgfcpeHcqRA4ZuU3UXDwxQGLVqjqceIWsZFk/iH4HNR44jEiPwIX4nceUsnBSkx81 uBxLSjAcLVujex6DPLvJ+7Ea2TJIeOrqSsKC7JyhnBaUlfmPPDj7kSTWp3vLffWRzlJe fu/WfjmKuUCWZJV1qlKDvP2+LVlbk+up3FUwo84t5V0gJ05yQHg3epB+ZSMqw9/90ZVS WM4w== X-Gm-Message-State: ALoCoQmriik0fbG17rpi0y6SuP6mJXAvgsZOx3eOrlVST32zeIWD8BeQBHOh+fwOX2ag6xGWsE9j X-Received: by 10.112.50.197 with SMTP id e5mr609726lbo.4.1390908170173; Tue, 28 Jan 2014 03:22:50 -0800 (PST) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginm.net. [82.1.113.198]) by mx.google.com with ESMTPSA id a8sm22366424lae.5.2014.01.28.03.22.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jan 2014 03:22:49 -0800 (PST) From: Will Newton To: qemu-devel@nongnu.org Date: Tue, 28 Jan 2014 11:22:30 +0000 Message-Id: <1390908155-23475-6-git-send-email-will.newton@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1390908155-23475-1-git-send-email-will.newton@linaro.org> References: <1390908155-23475-1-git-send-email-will.newton@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.45 Cc: Peter Maydell , patches@linaro.org Subject: [Qemu-devel] [PATCH v2 06/11] target-arm: Add support for AArch32 SIMD VRINTX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: Will Newton Reviewed-by: Peter Maydell --- target-arm/translate.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9eb5b92..c179817 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4709,6 +4709,7 @@ static const uint8_t neon_3r_sizes[] = { #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ #define NEON_2RM_VSHLL 38 +#define NEON_2RM_VRINTX 41 #define NEON_2RM_VCVT_F16_F32 44 #define NEON_2RM_VCVT_F32_F16 46 #define NEON_2RM_VRECPE 56 @@ -4724,7 +4725,7 @@ static int neon_2rm_is_float_op(int op) { /* Return true if this neon 2reg-misc op is float-to-float */ return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || - op >= NEON_2RM_VRECPE_F); + op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F); } /* Each entry in this array has bit n set if the insn allows @@ -4768,6 +4769,7 @@ static const uint8_t neon_2rm_sizes[] = { [NEON_2RM_VMOVN] = 0x7, [NEON_2RM_VQMOVN] = 0x7, [NEON_2RM_VSHLL] = 0x7, + [NEON_2RM_VRINTX] = 0x4, [NEON_2RM_VCVT_F16_F32] = 0x2, [NEON_2RM_VCVT_F32_F16] = 0x2, [NEON_2RM_VRECPE] = 0x4, @@ -6480,6 +6482,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins } neon_store_reg(rm, pass, tmp2); break; + case NEON_2RM_VRINTX: + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus); + tcg_temp_free_ptr(fpstatus); + break; + } case NEON_2RM_VRECPE: gen_helper_recpe_u32(tmp, tmp, cpu_env); break;