From patchwork Tue Jan 14 16:43:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 310795 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44D5C2C0079 for ; Wed, 15 Jan 2014 03:47:32 +1100 (EST) Received: from localhost ([::1]:49243 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W379F-0007nZ-0z for incoming@patchwork.ozlabs.org; Tue, 14 Jan 2014 11:47:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41123) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W375S-00027R-Ee for qemu-devel@nongnu.org; Tue, 14 Jan 2014 11:43:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W375M-0001Jf-K2 for qemu-devel@nongnu.org; Tue, 14 Jan 2014 11:43:34 -0500 Received: from mail-wg0-f48.google.com ([74.125.82.48]:32982) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W375M-0001Iz-Ee for qemu-devel@nongnu.org; Tue, 14 Jan 2014 11:43:28 -0500 Received: by mail-wg0-f48.google.com with SMTP id x13so625965wgg.15 for ; Tue, 14 Jan 2014 08:43:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=16zWgnJBoRtgn2pnL7GqYrgkx+iEF1Rm7aLf2Cz8kaE=; b=ADVPWYrMMzs2+H+zAaLA8jRuO1uDxHPqRjAV975VRX2igACifn+gJ5iLkjuBxkHPst EUu9vAS5cRGAzjI9DL0uUuAW4Ca1YLtDcFiZySRTs9jUNwBW35OhKScQVr3Sh/cDcB3z qKGAPIZoWivOG4x4BVh65j3JzxDr6FDVnw8PwLoWmRmLWXlJUEeb5lxCEVAnNKUIxEQO 057tjjZ+k2AZxXxpO+GplIT0idYBYm+Q0hglbAm6MHEXztMV0FiE/3zEyOW632XYLwoh im2BS6birFSaeQJjPyocDpcO5cruZjmo0Tm0xrZKnDQnP38SyDIN3dNcJdxfZ/Zw7/R7 R2kQ== X-Gm-Message-State: ALoCoQk/jI3fgQioXuZVKkrF3nBb1/oWUKc3YkARx0HvJg/VjR0M455+CmQX8xLIllWXaOIh65fY X-Received: by 10.180.206.104 with SMTP id ln8mr3927602wic.13.1389717807715; Tue, 14 Jan 2014 08:43:27 -0800 (PST) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginm.net. [82.1.113.198]) by mx.google.com with ESMTPSA id jw4sm971156wjc.20.2014.01.14.08.43.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jan 2014 08:43:27 -0800 (PST) From: Will Newton To: qemu-devel@nongnu.org Date: Tue, 14 Jan 2014 16:43:07 +0000 Message-Id: <1389717790-30860-7-git-send-email-will.newton@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1389717790-30860-1-git-send-email-will.newton@linaro.org> References: <1389717790-30860-1-git-send-email-will.newton@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.48 Cc: Peter Maydell Subject: [Qemu-devel] [PATCH 6/9] target-arm: Add support for AArch32 SIMD VRINTX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: Will Newton Reviewed-by: Peter Maydell --- target-arm/translate.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 5108f6b..b6d11db 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4709,6 +4709,7 @@ static const uint8_t neon_3r_sizes[] = { #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ #define NEON_2RM_VSHLL 38 +#define NEON_2RM_VRINTX 41 #define NEON_2RM_VCVT_F16_F32 44 #define NEON_2RM_VCVT_F32_F16 46 #define NEON_2RM_VRECPE 56 @@ -4724,7 +4725,7 @@ static int neon_2rm_is_float_op(int op) { /* Return true if this neon 2reg-misc op is float-to-float */ return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || - op >= NEON_2RM_VRECPE_F); + op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F); } /* Each entry in this array has bit n set if the insn allows @@ -4768,6 +4769,7 @@ static const uint8_t neon_2rm_sizes[] = { [NEON_2RM_VMOVN] = 0x7, [NEON_2RM_VQMOVN] = 0x7, [NEON_2RM_VSHLL] = 0x7, + [NEON_2RM_VRINTX] = 0x4, [NEON_2RM_VCVT_F16_F32] = 0x2, [NEON_2RM_VCVT_F32_F16] = 0x2, [NEON_2RM_VRECPE] = 0x4, @@ -6480,6 +6482,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins } neon_store_reg(rm, pass, tmp2); break; + case NEON_2RM_VRINTX: + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus); + tcg_temp_free_ptr(fpstatus); + break; + } case NEON_2RM_VRECPE: gen_helper_recpe_u32(tmp, tmp, cpu_env); break;