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X-Received-From: 2607:f8b0:400d:c00::22f Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V6 PATCH 11/18] target-ppc: VSX Stage 4: add xsrsqrtesp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX Scalar Reciprocal Square Root Estimate Single Precision (xsrsqrtesp) instruction. The existing VSX_RSQRTE() macro is modified to support rounding of the intermediate double-precision result to single precision. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- V2: Updated conversion to single precision range. target-ppc/fpu_helper.c | 13 +++++++++---- target-ppc/helper.h | 1 + target-ppc/translate.c | 2 ++ 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index fec9d1b..33da462 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -2018,7 +2018,7 @@ VSX_SQRT(xvsqrtsp, 4, float32, f32, 0, 0) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_RSQRTE(op, nels, tp, fld, sfprf) \ +#define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xb; \ @@ -2043,6 +2043,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ \ + if (r2sp) { \ + xt.fld[i] = helper_frsp(env, xt.fld[i]); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[i], sfprf); \ } \ @@ -2052,9 +2056,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1) -VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0) -VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0) +VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1, 0) +VSX_RSQRTE(xsrsqrtesp, 1, float64, f64, 1, 1) +VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0, 0) +VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0, 0) static inline int ppc_float32_get_unbiased_exp(float32 f) { diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 0192043..84c6ee1 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -292,6 +292,7 @@ DEF_HELPER_2(xsmulsp, void, env, i32) DEF_HELPER_2(xsdivsp, void, env, i32) DEF_HELPER_2(xsresp, void, env, i32) DEF_HELPER_2(xssqrtsp, void, env, i32) +DEF_HELPER_2(xsrsqrtesp, void, env, i32) DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f4c1f42..950c02e 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7364,6 +7364,7 @@ GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) @@ -10177,6 +10178,7 @@ GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), +GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),