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[50.194.63.110]) by mx.google.com with ESMTPSA id d7sm22444571qam.5.2014.01.07.13.02.22 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jan 2014 13:02:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 7 Jan 2014 13:00:31 -0800 Message-Id: <1389128439-10067-42-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1389128439-10067-1-git-send-email-rth@twiddle.net> References: <1389128439-10067-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c02::22f Cc: aliguori@amazon.com Subject: [Qemu-devel] [PULL 41/49] target-i386: Tidy cpu_regs initialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-i386/translate.c | 87 ++++++++++++++++++++----------------------------- 1 file changed, 36 insertions(+), 51 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9baeffa..5a594b9 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7823,6 +7823,37 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, void optimize_flags_init(void) { + static const char reg_names[CPU_NB_REGS][4] = { +#ifdef TARGET_X86_64 + [R_EAX] = "rax", + [R_EBX] = "rbx", + [R_ECX] = "rcx", + [R_EDX] = "rdx", + [R_ESI] = "rsi", + [R_EDI] = "rdi", + [R_EBP] = "rbp", + [R_ESP] = "rsp", + [8] = "r8", + [9] = "r9", + [10] = "r10", + [11] = "r11", + [12] = "r12", + [13] = "r13", + [14] = "r14", + [15] = "r15", +#else + [R_EAX] = "eax", + [R_EBX] = "ebx", + [R_ECX] = "ecx", + [R_EDX] = "edx", + [R_ESI] = "esi", + [R_EDI] = "edi", + [R_EBP] = "ebp", + [R_ESP] = "esp", +#endif + }; + int i; + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUX86State, cc_op), "cc_op"); @@ -7833,57 +7864,11 @@ void optimize_flags_init(void) cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src2), "cc_src2"); -#ifdef TARGET_X86_64 - cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_EAX]), "rax"); - cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_ECX]), "rcx"); - cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_EDX]), "rdx"); - cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_EBX]), "rbx"); - cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_ESP]), "rsp"); - cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_EBP]), "rbp"); - cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_ESI]), "rsi"); - cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[R_EDI]), "rdi"); - cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[8]), "r8"); - cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[9]), "r9"); - cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[10]), "r10"); - cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[11]), "r11"); - cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[12]), "r12"); - cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[13]), "r13"); - cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[14]), "r14"); - cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0, - offsetof(CPUX86State, regs[15]), "r15"); -#else - cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_EAX]), "eax"); - cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_ECX]), "ecx"); - cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_EDX]), "edx"); - cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_EBX]), "ebx"); - cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_ESP]), "esp"); - cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_EBP]), "ebp"); - cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_ESI]), "esi"); - cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUX86State, regs[R_EDI]), "edi"); -#endif + for (i = 0; i < CPU_NB_REGS; ++i) { + cpu_regs[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUX86State, regs[i]), + reg_names[i]); + } } /* generate intermediate code in gen_opc_buf and gen_opparam_buf for