From patchwork Tue Dec 24 17:04:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 305049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DC5D62C00B7 for ; Wed, 25 Dec 2013 05:32:04 +1100 (EST) Received: from localhost ([::1]:39644 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvVUo-0004kF-Iu for incoming@patchwork.ozlabs.org; Tue, 24 Dec 2013 12:10:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvVPQ-000605-NG for qemu-devel@nongnu.org; Tue, 24 Dec 2013 12:04:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvVPL-00045g-8X for qemu-devel@nongnu.org; Tue, 24 Dec 2013 12:04:44 -0500 Received: from cantor2.suse.de ([195.135.220.15]:54393 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvVPL-00044c-3V for qemu-devel@nongnu.org; Tue, 24 Dec 2013 12:04:39 -0500 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id D95B7AC19; Tue, 24 Dec 2013 17:04:38 +0000 (UTC) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Tue, 24 Dec 2013 18:04:17 +0100 Message-Id: <1387904675-7962-7-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1387904675-7962-1-git-send-email-afaerber@suse.de> References: <1387904675-7962-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.135.220.15 Cc: "Michael S. Tsirkin" , Markus Armbruster , Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PULL v2 06/24] ich9: Document why cannot_instantiate_with_device_add_yet X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Markus Armbruster An ICH9 southbridge contains several PCI devices, some of them with multiple functions. We model each function as a separate qdev. Two of them need some special wiring set up in pc_q35_init() to work: the LPC controller at 00:1f.0, and the SMBus controller at 00:1f.3. Signed-off-by: Markus Armbruster Reviewed-by: Peter Maydell Signed-off-by: Andreas Färber --- hw/i2c/smbus_ich9.c | 6 +++++- hw/isa/lpc_ich9.c | 7 +++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index c1ffa34..8d47eaf 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -97,11 +97,15 @@ static void ich9_smb_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6; k->revision = ICH9_A2_SMB_REVISION; k->class_id = PCI_CLASS_SERIAL_SMBUS; - dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain why */ dc->vmsd = &vmstate_ich9_smbus; dc->desc = "ICH9 SMBUS Bridge"; k->init = ich9_smbus_initfn; k->config_write = ich9_smbus_write_config; + /* + * Reason: part of ICH9 southbridge, needs to be wired up by + * pc_q35_init() + */ + dc->cannot_instantiate_with_device_add_yet = true; } i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index c1ca4d4..51ce12d 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -644,14 +644,17 @@ static void ich9_lpc_class_init(ObjectClass *klass, void *data) dc->reset = ich9_lpc_reset; k->init = ich9_lpc_initfn; dc->vmsd = &vmstate_ich9_lpc; - dc->cannot_instantiate_with_device_add_yet = true; /* FIXME explain why */ k->config_write = ich9_lpc_config_write; dc->desc = "ICH9 LPC bridge"; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; k->revision = ICH9_A2_LPC_REVISION; k->class_id = PCI_CLASS_BRIDGE_ISA; - + /* + * Reason: part of ICH9 southbridge, needs to be wired up by + * pc_q35_init() + */ + dc->cannot_instantiate_with_device_add_yet = true; } static const TypeInfo ich9_lpc_info = {