From patchwork Fri Dec 20 01:00:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 303840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BC37E2C00D2 for ; Fri, 20 Dec 2013 13:40:04 +1100 (EST) Received: from localhost ([::1]:47155 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtoZn-0004Ql-Uj for incoming@patchwork.ozlabs.org; Thu, 19 Dec 2013 20:08:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42186) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtoSl-0004qc-PE for qemu-devel@nongnu.org; Thu, 19 Dec 2013 20:01:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtoSa-0002P5-9f for qemu-devel@nongnu.org; Thu, 19 Dec 2013 20:01:11 -0500 Received: from cantor2.suse.de ([195.135.220.15]:50726 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtoSa-0002Nt-30; Thu, 19 Dec 2013 20:01:00 -0500 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 047CAAC2B; Fri, 20 Dec 2013 01:00:58 +0000 (UTC) From: Alexander Graf To: QEMU Developers Date: Fri, 20 Dec 2013 02:00:48 +0100 Message-Id: <1387501254-60704-27-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1387501254-60704-1-git-send-email-agraf@suse.de> References: <1387501254-60704-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.135.220.15 Cc: Tom Musta , "qemu-ppc@nongnu.org" , Anthony Liguori Subject: [Qemu-devel] [PULL 26/32] Add xxspltw X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Tom Musta This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson Signed-off-by: Alexander Graf --- target-ppc/translate.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e5d7f9d..f342468 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -499,6 +499,7 @@ EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); EXTRACT_HELPER(DM, 8, 2); +EXTRACT_HELPER(UIM, 16, 2); /*****************************************************************************/ /* PowerPC instructions table */ @@ -7358,6 +7359,35 @@ static void gen_xxsel(DisasContext * ctx) tcg_temp_free(c); } +static void gen_xxspltw(DisasContext *ctx) +{ + TCGv_i64 b, b2; + TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? + cpu_vsrl(xB(ctx->opcode)) : + cpu_vsrh(xB(ctx->opcode)); + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + + b = tcg_temp_new(); + b2 = tcg_temp_new(); + + if (UIM(ctx->opcode) & 1) { + tcg_gen_ext32u_i64(b, vsr); + } else { + tcg_gen_shri_i64(b, vsr, 32); + } + + tcg_gen_shli_i64(b2, b, 32); + tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); + tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); + + tcg_temp_free(b); + tcg_temp_free(b2); +} + /*** SPE extension ***/ /* Register moves */ @@ -9872,6 +9902,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), +GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), #define GEN_XXSEL_ROW(opc3) \ GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \