From patchwork Tue Dec 17 20:29:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 302491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 94E192C0086 for ; Wed, 18 Dec 2013 08:05:59 +1100 (EST) Received: from localhost ([::1]:35286 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1JD-00018d-V4 for incoming@patchwork.ozlabs.org; Tue, 17 Dec 2013 15:32:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52896) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1Gj-0005z4-Fm for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:29:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vt1Ge-00035D-1P for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:29:29 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43626) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1Gd-00034c-Qg for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:29:23 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Vt1Gd-0003Io-Gu; Tue, 17 Dec 2013 20:29:23 +0000 From: Peter Maydell To: Anthony Liguori Date: Tue, 17 Dec 2013 20:29:03 +0000 Message-Id: <1387312160-12318-46-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> References: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Graf This adds support for the C5.6.147 RBIT instruction. Signed-off-by: Alexander Graf [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, splitting REV into a separate patch] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/helper-a64.c | 18 ++++++++++++++++++ target-arm/helper-a64.h | 1 + target-arm/translate-a64.c | 20 ++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index e4c5346..cccaac6 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -49,3 +49,21 @@ uint64_t HELPER(clz64)(uint64_t x) { return clz64(x); } + +uint64_t HELPER(rbit64)(uint64_t x) +{ + /* assign the correct byte position */ + x = bswap64(x); + + /* assign the correct nibble position */ + x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4) + | ((x & 0x0f0f0f0f0f0f0f0fULL) << 4); + + /* assign the correct bit position */ + x = ((x & 0x8888888888888888ULL) >> 3) + | ((x & 0x4444444444444444ULL) >> 1) + | ((x & 0x2222222222222222ULL) << 1) + | ((x & 0x1111111111111111ULL) << 3); + + return x; +} diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index b10b6c3..9959139 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -19,3 +19,4 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64) +DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index e5481da..0ed21fc 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1062,6 +1062,24 @@ static void handle_clz(DisasContext *s, unsigned int sf, } } +static void handle_rbit(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + gen_helper_rbit64(tcg_rd, tcg_rn); + } else { + TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); + gen_helper_rbit(tcg_tmp32, tcg_tmp32); + tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); + tcg_temp_free_i32(tcg_tmp32); + } +} + /* C3.5.7 Data-processing (1 source) * 31 30 29 28 21 20 16 15 10 9 5 4 0 * +----+---+---+-----------------+---------+--------+------+------+ @@ -1084,6 +1102,8 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) switch (opcode) { case 0: /* RBIT */ + handle_rbit(s, sf, rn, rd); + break; case 1: /* REV16 */ case 2: /* REV32 */ case 3: /* REV64 */