From patchwork Fri Nov 29 02:59:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 295076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 11D732C0087 for ; Fri, 29 Nov 2013 14:03:20 +1100 (EST) Received: from localhost ([::1]:44934 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEMP-0003Ms-Fd for incoming@patchwork.ozlabs.org; Thu, 28 Nov 2013 22:03:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEKU-0000na-FE for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmEKO-0001wW-H0 for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:18 -0500 Received: from mail-pb0-x230.google.com ([2607:f8b0:400e:c01::230]:60235) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEKN-0001wR-OQ for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:12 -0500 Received: by mail-pb0-f48.google.com with SMTP id md12so13593631pbc.35 for ; Thu, 28 Nov 2013 19:01:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=XT4bqqBi1DIHkAUNEhWFaIJkiILpPN4iNJ0EnYDUUFE=; b=EgJBXj6xZvA5WQ9Cey5xQfQDJ2Pq5262DFNgt3r5ololiBs7xbym95PgaPRznAH7b0 DJt5u8wKjLvCZvpBP7u0d1K7011l4QL35d0aprjuc7BMcfP4/jmcgXX0LBX/QyyF947o GpSaM6Kf80flVqGyBhOld435qRy1rrpMd6QFCgWusobzFdEm5bZtO/KnmgOOkOJvouuN rLLNYeo6Lnq4RdctujvTFsPu5ug/523RpubZufJcUnnXMuOzZlxQfVDNSkof7KwVLAhE 56PTLSiTiKWd/797R/kTxMoemZuf7oASvhnSI2/GnIO927QOlJiq2qB1FIghV6lajiRo pwrA== X-Received: by 10.66.182.199 with SMTP id eg7mr25539936pac.135.1385694070733; Thu, 28 Nov 2013 19:01:10 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.01.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:01:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 29 Nov 2013 15:59:49 +1300 Message-Id: <1385694047-6116-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v2 02/60] target-i386: Push DisasContext into load/store helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Rather than add s->mem_index into a combined size+mem_index argument, pass the context down. This will allow cleaning up s->mem_index later. Signed-off-by: Richard Henderson --- target-i386/translate.c | 331 +++++++++++++++++++++++++----------------------- 1 file changed, 170 insertions(+), 161 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 7916e5b..8c5c16b 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -584,9 +584,9 @@ static inline void gen_op_addq_A0_reg_sN(int shift, int reg) } #endif -static inline void gen_op_lds_T0_A0(int idx) +static inline void gen_op_lds_T0_A0(DisasContext *s, int idx) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; switch(idx & 3) { case OT_BYTE: tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index); @@ -601,9 +601,9 @@ static inline void gen_op_lds_T0_A0(int idx) } } -static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) +static inline void gen_op_ld_v(DisasContext *s, int idx, TCGv t0, TCGv a0) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; switch(idx & 3) { case OT_BYTE: tcg_gen_qemu_ld8u(t0, a0, mem_index); @@ -625,24 +625,24 @@ static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0) } /* XXX: always use ldu or lds */ -static inline void gen_op_ld_T0_A0(int idx) +static inline void gen_op_ld_T0_A0(DisasContext *s, int idx) { - gen_op_ld_v(idx, cpu_T[0], cpu_A0); + gen_op_ld_v(s, idx, cpu_T[0], cpu_A0); } -static inline void gen_op_ldu_T0_A0(int idx) +static inline void gen_op_ldu_T0_A0(DisasContext *s, int idx) { - gen_op_ld_v(idx, cpu_T[0], cpu_A0); + gen_op_ld_v(s, idx, cpu_T[0], cpu_A0); } -static inline void gen_op_ld_T1_A0(int idx) +static inline void gen_op_ld_T1_A0(DisasContext *s, int idx) { - gen_op_ld_v(idx, cpu_T[1], cpu_A0); + gen_op_ld_v(s, idx, cpu_T[1], cpu_A0); } -static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) +static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; switch(idx & 3) { case OT_BYTE: tcg_gen_qemu_st8(t0, a0, mem_index); @@ -663,14 +663,14 @@ static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0) } } -static inline void gen_op_st_T0_A0(int idx) +static inline void gen_op_st_T0_A0(DisasContext *s, int idx) { - gen_op_st_v(idx, cpu_T[0], cpu_A0); + gen_op_st_v(s, idx, cpu_T[0], cpu_A0); } -static inline void gen_op_st_T1_A0(int idx) +static inline void gen_op_st_T1_A0(DisasContext *s, int idx) { - gen_op_st_v(idx, cpu_T[1], cpu_A0); + gen_op_st_v(s, idx, cpu_T[1], cpu_A0); } static inline void gen_jmp_im(target_ulong pc) @@ -867,9 +867,9 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, static inline void gen_movs(DisasContext *s, int ot) { gen_string_movl_A0_ESI(s); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); gen_string_movl_A0_EDI(s); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_op_add_reg_T0(s->aflag, R_EDI); @@ -1294,7 +1294,7 @@ static inline void gen_stos(DisasContext *s, int ot) { gen_op_mov_TN_reg(OT_LONG, 0, R_EAX); gen_string_movl_A0_EDI(s); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); } @@ -1302,7 +1302,7 @@ static inline void gen_stos(DisasContext *s, int ot) static inline void gen_lods(DisasContext *s, int ot) { gen_string_movl_A0_ESI(s); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); gen_op_mov_reg_T0(ot, R_EAX); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); @@ -1311,7 +1311,7 @@ static inline void gen_lods(DisasContext *s, int ot) static inline void gen_scas(DisasContext *s, int ot) { gen_string_movl_A0_EDI(s); - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); gen_op(s, OP_CMPL, ot, R_EAX); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); @@ -1320,7 +1320,7 @@ static inline void gen_scas(DisasContext *s, int ot) static inline void gen_cmps(DisasContext *s, int ot) { gen_string_movl_A0_EDI(s); - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); gen_string_movl_A0_ESI(s); gen_op(s, OP_CMPL, ot, OR_TMP0); gen_op_movl_T0_Dshift(ot); @@ -1336,12 +1336,12 @@ static inline void gen_ins(DisasContext *s, int ot) /* Note: we must do this dummy write first to be restartable in case of page fault. */ gen_op_movl_T0_0(); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); if (use_icount) @@ -1353,7 +1353,7 @@ static inline void gen_outs(DisasContext *s, int ot) if (use_icount) gen_io_start(); gen_string_movl_A0_ESI(s); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); gen_op_mov_TN_reg(OT_WORD, 1, R_EDX); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); @@ -1473,7 +1473,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) { gen_op_mov_TN_reg(ot, 0, d); } else { - gen_op_ld_T0_A0(ot + s1->mem_index); + gen_op_ld_T0_A0(s1, ot); } switch(op) { case OP_ADCL: @@ -1483,7 +1483,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update3_cc(cpu_tmp4); set_cc_op(s1, CC_OP_ADCB + ot); break; @@ -1494,7 +1494,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update3_cc(cpu_tmp4); set_cc_op(s1, CC_OP_SBBB + ot); break; @@ -1503,7 +1503,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update2_cc(); set_cc_op(s1, CC_OP_ADDB + ot); break; @@ -1513,7 +1513,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update2_cc(); set_cc_op(s1, CC_OP_SUBB + ot); break; @@ -1523,7 +1523,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update1_cc(); set_cc_op(s1, CC_OP_LOGICB + ot); break; @@ -1532,7 +1532,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update1_cc(); set_cc_op(s1, CC_OP_LOGICB + ot); break; @@ -1541,7 +1541,7 @@ static void gen_op(DisasContext *s1, int op, int ot, int d) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); gen_op_update1_cc(); set_cc_op(s1, CC_OP_LOGICB + ot); break; @@ -1560,7 +1560,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c) if (d != OR_TMP0) gen_op_mov_TN_reg(ot, 0, d); else - gen_op_ld_T0_A0(ot + s1->mem_index); + gen_op_ld_T0_A0(s1, ot); gen_compute_eflags_c(s1, cpu_cc_src); if (c > 0) { tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1); @@ -1572,7 +1572,7 @@ static void gen_inc(DisasContext *s1, int ot, int d, int c) if (d != OR_TMP0) gen_op_mov_reg_T0(ot, d); else - gen_op_st_T0_A0(ot + s1->mem_index); + gen_op_st_T0_A0(s1, ot); tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]); } @@ -1628,7 +1628,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, /* load */ if (op1 == OR_TMP0) { - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, op1); } @@ -1653,7 +1653,7 @@ static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, /* store */ if (op1 == OR_TMP0) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { gen_op_mov_reg_T0(ot, op1); } @@ -1668,7 +1668,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, /* load */ if (op1 == OR_TMP0) - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); else gen_op_mov_TN_reg(ot, 0, op1); @@ -1692,7 +1692,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2, /* store */ if (op1 == OR_TMP0) - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); else gen_op_mov_reg_T0(ot, op1); @@ -1719,7 +1719,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right) /* load */ if (op1 == OR_TMP0) { - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, op1); } @@ -1760,7 +1760,7 @@ static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right) /* store */ if (op1 == OR_TMP0) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { gen_op_mov_reg_T0(ot, op1); } @@ -1809,7 +1809,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, /* load */ if (op1 == OR_TMP0) { - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, op1); } @@ -1855,7 +1855,7 @@ static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2, /* store */ if (op1 == OR_TMP0) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { gen_op_mov_reg_T0(ot, op1); } @@ -1891,7 +1891,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, /* load */ if (op1 == OR_TMP0) - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); else gen_op_mov_TN_reg(ot, 0, op1); @@ -1932,7 +1932,7 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, } /* store */ if (op1 == OR_TMP0) - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); else gen_op_mov_reg_T0(ot, op1); } @@ -1946,7 +1946,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1, /* load */ if (op1 == OR_TMP0) { - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, op1); } @@ -2014,7 +2014,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1, /* store */ if (op1 == OR_TMP0) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { gen_op_mov_reg_T0(ot, op1); } @@ -2363,9 +2363,9 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, if (is_store) { if (reg != OR_TMP0) gen_op_mov_TN_reg(ot, 0, reg); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); if (reg != OR_TMP0) gen_op_mov_reg_T0(ot, reg); } @@ -2566,10 +2566,10 @@ static void gen_push_T0(DisasContext *s) gen_op_movq_A0_reg(R_ESP); if (s->dflag) { gen_op_addq_A0_im(-8); - gen_op_st_T0_A0(OT_QUAD + s->mem_index); + gen_op_st_T0_A0(s, OT_QUAD); } else { gen_op_addq_A0_im(-2); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); } gen_op_mov_reg_A0(2, R_ESP); } else @@ -2590,7 +2590,7 @@ static void gen_push_T0(DisasContext *s) tcg_gen_mov_tl(cpu_T[1], cpu_A0); gen_op_addl_A0_seg(s, R_SS); } - gen_op_st_T0_A0(s->dflag + 1 + s->mem_index); + gen_op_st_T0_A0(s, s->dflag + 1); if (s->ss32 && !s->addseg) gen_op_mov_reg_A0(1, R_ESP); else @@ -2607,10 +2607,10 @@ static void gen_push_T1(DisasContext *s) gen_op_movq_A0_reg(R_ESP); if (s->dflag) { gen_op_addq_A0_im(-8); - gen_op_st_T1_A0(OT_QUAD + s->mem_index); + gen_op_st_T1_A0(s, OT_QUAD); } else { gen_op_addq_A0_im(-2); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); } gen_op_mov_reg_A0(2, R_ESP); } else @@ -2629,7 +2629,7 @@ static void gen_push_T1(DisasContext *s) gen_op_andl_A0_ffff(); gen_op_addl_A0_seg(s, R_SS); } - gen_op_st_T1_A0(s->dflag + 1 + s->mem_index); + gen_op_st_T1_A0(s, s->dflag + 1); if (s->ss32 && !s->addseg) gen_op_mov_reg_A0(1, R_ESP); @@ -2644,7 +2644,7 @@ static void gen_pop_T0(DisasContext *s) #ifdef TARGET_X86_64 if (CODE64(s)) { gen_op_movq_A0_reg(R_ESP); - gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index); + gen_op_ld_T0_A0(s, s->dflag ? OT_QUAD : OT_WORD); } else #endif { @@ -2656,7 +2656,7 @@ static void gen_pop_T0(DisasContext *s) gen_op_andl_A0_ffff(); gen_op_addl_A0_seg(s, R_SS); } - gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index); + gen_op_ld_T0_A0(s, s->dflag + 1); } } @@ -2695,7 +2695,7 @@ static void gen_pusha(DisasContext *s) gen_op_addl_A0_seg(s, R_SS); for(i = 0;i < 8; i++) { gen_op_mov_TN_reg(OT_LONG, 0, 7 - i); - gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD + s->dflag); gen_op_addl_A0_im(2 << s->dflag); } gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP); @@ -2715,7 +2715,7 @@ static void gen_popa(DisasContext *s) for(i = 0;i < 8; i++) { /* ESP is not reloaded */ if (i != 3) { - gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index); + gen_op_ld_T0_A0(s, OT_WORD + s->dflag); gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i); } gen_op_addl_A0_im(2 << s->dflag); @@ -2739,7 +2739,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) /* push bp */ gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); if (level) { /* XXX: must save state */ gen_helper_enter64_level(cpu_env, tcg_const_i32(level), @@ -2764,7 +2764,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_addl_A0_seg(s, R_SS); /* push bp */ gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); if (level) { /* XXX: must save state */ gen_helper_enter_level(cpu_env, tcg_const_i32(level), @@ -2846,23 +2846,23 @@ static void gen_jmp(DisasContext *s, target_ulong eip) gen_jmp_tb(s, eip, 0); } -static inline void gen_ldq_env_A0(int idx, int offset) +static inline void gen_ldq_env_A0(DisasContext *s, int offset) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset); } -static inline void gen_stq_env_A0(int idx, int offset) +static inline void gen_stq_env_A0(DisasContext *s, int offset) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset); tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); } -static inline void gen_ldo_env_A0(int idx, int offset) +static inline void gen_ldo_env_A0(DisasContext *s, int offset) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index); tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); @@ -2870,9 +2870,9 @@ static inline void gen_ldo_env_A0(int idx, int offset) tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1))); } -static inline void gen_sto_env_A0(int idx, int offset) +static inline void gen_sto_env_A0(DisasContext *s, int offset) { - int mem_index = (idx >> 2) - 1; + int mem_index = (s->mem_index >> 2) - 1; tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0))); tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index); tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8); @@ -3312,7 +3312,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) goto illegal_op; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); + gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); break; case 0x1e7: /* movntdq */ case 0x02b: /* movntps */ @@ -3320,13 +3320,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod == 3) goto illegal_op; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); + gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); break; case 0x3f0: /* lddqu */ if (mod == 3) goto illegal_op; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); + gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); break; case 0x22b: /* movntss */ case 0x32b: /* movntsd */ @@ -3334,12 +3334,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, goto illegal_op; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (b1 & 1) { - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, - xmm_regs[reg])); + gen_stq_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, xmm_regs[reg].XMM_L(0))); - gen_op_st_T0_A0(OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, OT_LONG); } break; case 0x6e: /* movd mm, ea */ @@ -3377,7 +3376,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x6f: /* movq mm, ea */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); + gen_ldq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); } else { rm = (modrm & 7); tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, @@ -3394,7 +3393,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x26f: /* movdqu xmm, ea */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); + gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]), @@ -3404,7 +3403,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x210: /* movss xmm, ea */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_movl_T0_0(); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1))); @@ -3419,7 +3418,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x310: /* movsd xmm, ea */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_ldq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); gen_op_movl_T0_0(); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3))); @@ -3433,7 +3433,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x112: /* movlpd */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_ldq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); } else { /* movhlps */ rm = (modrm & 7) | REX_B(s); @@ -3444,7 +3445,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x212: /* movsldup */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); + gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)), @@ -3460,7 +3461,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x312: /* movddup */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_ldq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), @@ -3473,7 +3475,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x116: /* movhpd */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); + gen_ldq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(1))); } else { /* movlhps */ rm = (modrm & 7) | REX_B(s); @@ -3484,7 +3487,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x216: /* movshdup */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); + gen_ldo_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)), @@ -3549,7 +3552,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x27e: /* movq xmm, ea */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_ldq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)), @@ -3560,7 +3564,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x7f: /* movq ea, mm */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); + gen_stq_env_A0(s, offsetof(CPUX86State, fpregs[reg].mmx)); } else { rm = (modrm & 7); gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx), @@ -3575,7 +3579,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x27f: /* movdqu ea, xmm */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); + gen_sto_env_A0(s, offsetof(CPUX86State, xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]), @@ -3586,7 +3590,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); - gen_op_st_T0_A0(OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, OT_LONG); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), @@ -3596,7 +3600,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x311: /* movsd ea, xmm */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_stq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), @@ -3607,7 +3612,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x113: /* movlpd */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_stq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); } else { goto illegal_op; } @@ -3616,7 +3622,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x117: /* movhpd */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); + gen_stq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(1))); } else { goto illegal_op; } @@ -3682,7 +3689,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); - gen_ldq_env_A0(s->mem_index, op2_offset); + gen_ldq_env_A0(s, op2_offset); } else { rm = (modrm & 7); op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); @@ -3727,7 +3734,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,xmm_t0); - gen_ldo_env_A0(s->mem_index, op2_offset); + gen_ldo_env_A0(s, op2_offset); } else { rm = (modrm & 7) | REX_B(s); op2_offset = offsetof(CPUX86State,xmm_regs[rm]); @@ -3758,9 +3765,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if ((b >> 8) & 1) { - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); + gen_ldq_env_A0(s, offsetof(CPUX86State, xmm_t0.XMM_Q(0))); } else { - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); } op2_offset = offsetof(CPUX86State,xmm_t0); @@ -3823,7 +3830,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x1d6: /* movq ea, xmm */ if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); + gen_stq_env_A0(s, offsetof(CPUX86State, + xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)), @@ -3894,7 +3902,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */ - gen_ldq_env_A0(s->mem_index, op2_offset + + gen_ldq_env_A0(s, op2_offset + offsetof(XMMReg, XMM_Q(0))); break; case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */ @@ -3912,10 +3920,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(XMMReg, XMM_W(0))); break; case 0x2a: /* movntqda */ - gen_ldo_env_A0(s->mem_index, op1_offset); + gen_ldo_env_A0(s, op1_offset); return; default: - gen_ldo_env_A0(s->mem_index, op2_offset); + gen_ldo_env_A0(s, op2_offset); } } } else { @@ -3925,7 +3933,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } else { op2_offset = offsetof(CPUX86State,mmx_t0); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, op2_offset); + gen_ldq_env_A0(s, op2_offset); } } if (sse_fn_epp == SSE_SPECIAL) { @@ -4490,7 +4498,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } else { op2_offset = offsetof(CPUX86State,xmm_t0); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldo_env_A0(s->mem_index, op2_offset); + gen_ldo_env_A0(s, op2_offset); } } else { op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); @@ -4499,7 +4507,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } else { op2_offset = offsetof(CPUX86State,mmx_t0); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_ldq_env_A0(s->mem_index, op2_offset); + gen_ldq_env_A0(s, op2_offset); } } val = cpu_ldub_code(env, s->pc++); @@ -4572,14 +4580,15 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* specific case for SSE single instructions */ if (b1 == 2) { /* 32 bit access */ - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); } else { /* 64 bit access */ - gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0))); + gen_ldq_env_A0(s, offsetof(CPUX86State, + xmm_t0.XMM_D(0))); } } else { - gen_ldo_env_A0(s->mem_index, op2_offset); + gen_ldo_env_A0(s, op2_offset); } } else { rm = (modrm & 7) | REX_B(s); @@ -4590,7 +4599,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); - gen_ldq_env_A0(s->mem_index, op2_offset); + gen_ldq_env_A0(s, op2_offset); } else { rm = (modrm & 7); op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); @@ -4887,7 +4896,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = (modrm & 7) | REX_B(s); if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); } else if (op == OP_XORL && rm == reg) { goto xor_zero; } else { @@ -4975,7 +4984,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (op == 0) s->rip_offset = insn_const_size(ot); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, rm); } @@ -4990,7 +4999,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 2: /* not */ tcg_gen_not_tl(cpu_T[0], cpu_T[0]); if (mod != 3) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { gen_op_mov_reg_T0(ot, rm); } @@ -4998,7 +5007,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 3: /* neg */ tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); if (mod != 3) { - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } else { gen_op_mov_reg_T0(ot, rm); } @@ -5187,7 +5196,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (op >= 2 && op != 3 && op != 5) - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, rm); } @@ -5218,9 +5227,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_eob(s); break; case 3: /* lcall Ev */ - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); - gen_op_ldu_T0_A0(OT_WORD + s->mem_index); + gen_op_ldu_T0_A0(s, OT_WORD); do_lcall: if (s->pe && !s->vm86) { gen_update_cc_op(s); @@ -5244,9 +5253,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_eob(s); break; case 5: /* ljmp Ev */ - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); - gen_op_ldu_T0_A0(OT_WORD + s->mem_index); + gen_op_ldu_T0_A0(s, OT_WORD); do_ljmp: if (s->pe && !s->vm86) { gen_update_cc_op(s); @@ -5409,9 +5418,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_mov_TN_reg(ot, 0, reg); - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); gen_op_addl_T0_T1(); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); gen_op_mov_reg_T1(ot, reg); } gen_op_update2_cc(); @@ -5441,7 +5450,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_mov_tl(a0, cpu_A0); - gen_op_ld_v(ot + s->mem_index, t0, a0); + gen_op_ld_v(s, ot, t0, a0); rm = 0; /* avoid warning */ } label1 = gen_new_label(); @@ -5459,11 +5468,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* perform no-op store cycle like physical cpu; must be before changing accumulator to ensure idempotency if the store faults and the instruction is restarted */ - gen_op_st_v(ot + s->mem_index, t0, a0); + gen_op_st_v(s, ot, t0, a0); gen_op_mov_reg_v(ot, R_EAX, t0); tcg_gen_br(label2); gen_set_label(label1); - gen_op_st_v(ot + s->mem_index, t1, a0); + gen_op_st_v(s, ot, t1, a0); } gen_set_label(label2); tcg_gen_mov_tl(cpu_cc_src, t0); @@ -5671,7 +5680,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = insn_get(env, s, ot); gen_op_movl_T0_im(val); if (mod != 3) - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); else gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); break; @@ -5757,9 +5766,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (b & 8) { - gen_op_lds_T0_A0(ot + s->mem_index); + gen_op_lds_T0_A0(s, ot); } else { - gen_op_ldu_T0_A0(ot + s->mem_index); + gen_op_ldu_T0_A0(s, ot); } gen_op_mov_reg_T0(d_ot, reg); } @@ -5810,11 +5819,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } gen_add_A0_ds_seg(s); if ((b & 2) == 0) { - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); gen_op_mov_reg_T0(ot, R_EAX); } else { gen_op_mov_TN_reg(ot, 0, R_EAX); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); } } break; @@ -5838,7 +5847,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff); } gen_add_A0_ds_seg(s); - gen_op_ldu_T0_A0(OT_BYTE + s->mem_index); + gen_op_ldu_T0_A0(s, OT_BYTE); gen_op_mov_reg_T0(OT_BYTE, R_EAX); break; case 0xb0 ... 0xb7: /* mov R, Ib */ @@ -5895,8 +5904,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* for xchg, lock is implicit */ if (!(prefixes & PREFIX_LOCK)) gen_helper_lock(); - gen_op_ld_T1_A0(ot + s->mem_index); - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); + gen_op_st_T0_A0(s, ot); if (!(prefixes & PREFIX_LOCK)) gen_helper_unlock(); gen_op_mov_reg_T1(ot, reg); @@ -5926,10 +5935,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod == 3) goto illegal_op; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_T1_A0(ot + s->mem_index); + gen_op_ld_T1_A0(s, ot); gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); /* load the segment first to handle exceptions properly */ - gen_op_ldu_T0_A0(OT_WORD + s->mem_index); + gen_op_ldu_T0_A0(s, OT_WORD); gen_movl_seg_T0(s, op, pc_start - s->cs_base); /* then put the data */ gen_op_mov_reg_T1(ot, reg); @@ -6053,12 +6062,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch(op >> 4) { case 0: - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32); break; case 1: - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); break; @@ -6069,7 +6078,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 3: default: - gen_op_lds_T0_A0(OT_WORD + s->mem_index); + gen_op_lds_T0_A0(s, OT_WORD); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32); break; @@ -6092,12 +6101,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0: switch(op >> 4) { case 0: - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32); break; case 1: - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); break; @@ -6108,7 +6117,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 3: default: - gen_op_lds_T0_A0(OT_WORD + s->mem_index); + gen_op_lds_T0_A0(s, OT_WORD); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32); break; @@ -6120,7 +6129,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 1: gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, OT_LONG); break; case 2: gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); @@ -6131,7 +6140,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, default: gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); break; } gen_helper_fpop(cpu_env); @@ -6141,12 +6150,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0: gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, OT_LONG); break; case 1: gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, OT_LONG); break; case 2: gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); @@ -6157,7 +6166,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, default: gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); break; } if ((op & 7) == 3) @@ -6171,7 +6180,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag)); break; case 0x0d: /* fldcw mem */ - gen_op_ld_T0_A0(OT_WORD + s->mem_index); + gen_op_ld_T0_A0(s, OT_WORD); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_fldcw(cpu_env, cpu_tmp2_i32); break; @@ -6183,7 +6192,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x0f: /* fnstcw mem */ gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); break; case 0x1d: /* fldt mem */ gen_update_cc_op(s); @@ -6209,7 +6218,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x2f: /* fnstsw mem */ gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); break; case 0x3c: /* fbld */ gen_update_cc_op(s); @@ -6780,7 +6789,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_stack_A0(s); /* pop offset */ - gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); + gen_op_ld_T0_A0(s, 1 + s->dflag); if (s->dflag == 0) gen_op_andl_T0_ffff(); /* NOTE: keeping EIP updated is not a problem in case of @@ -6788,7 +6797,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_jmp_T0(); /* pop selector */ gen_op_addl_A0_im(2 << s->dflag); - gen_op_ld_T0_A0(1 + s->dflag + s->mem_index); + gen_op_ld_T0_A0(s, 1 + s->dflag); gen_op_movl_seg_T0_vm(R_CS); /* add stack offset */ gen_stack_update(s, val + (4 << s->dflag)); @@ -7035,7 +7044,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod != 3) { s->rip_offset = 1; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, rm); } @@ -7071,7 +7080,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot); tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); - gen_op_ld_T0_A0(ot + s->mem_index); + gen_op_ld_T0_A0(s, ot); } else { gen_op_mov_TN_reg(ot, 0, rm); } @@ -7106,7 +7115,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, set_cc_op(s, CC_OP_SARB + ot); if (op != 0) { if (mod != 3) - gen_op_st_T0_A0(ot + s->mem_index); + gen_op_st_T0_A0(s, ot); else gen_op_mov_reg_T0(ot, rm); tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); @@ -7571,12 +7580,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); if (!s->dflag) gen_op_andl_T0_im(0xffffff); - gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, CODE64(s) + OT_LONG); break; case 1: if (mod == 3) { @@ -7634,12 +7643,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); - gen_op_st_T0_A0(OT_WORD + s->mem_index); + gen_op_st_T0_A0(s, OT_WORD); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); if (!s->dflag) gen_op_andl_T0_im(0xffffff); - gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, CODE64(s) + OT_LONG); } break; case 2: /* lgdt */ @@ -7734,9 +7743,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_svm_check_intercept(s, pc_start, op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_T1_A0(OT_WORD + s->mem_index); + gen_op_ld_T1_A0(s, OT_WORD); gen_add_A0_im(s, 2); - gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, CODE64(s) + OT_LONG); if (!s->dflag) gen_op_andl_T0_im(0xffffff); if (op == 2) { @@ -7855,9 +7864,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (d_ot == OT_QUAD) { - gen_op_lds_T0_A0(OT_LONG + s->mem_index); + gen_op_lds_T0_A0(s, OT_LONG); } else { - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); } gen_op_mov_reg_T0(d_ot, reg); } @@ -7879,7 +7888,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, rm = modrm & 7; if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); + gen_op_ld_v(s, ot, t0, cpu_A0); a0 = tcg_temp_local_new(); tcg_gen_mov_tl(a0, cpu_A0); } else { @@ -7897,7 +7906,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tcg_gen_movi_tl(t2, CC_Z); gen_set_label(label1); if (mod != 3) { - gen_op_st_v(ot + s->mem_index, t0, a0); + gen_op_st_v(s, ot, t0, a0); tcg_temp_free(a0); } else { gen_op_mov_reg_v(ot, rm, t0); @@ -8105,12 +8114,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, goto illegal_op; gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (op == 2) { - gen_op_ld_T0_A0(OT_LONG + s->mem_index); + gen_op_ld_T0_A0(s, OT_LONG); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); - gen_op_st_T0_A0(OT_LONG + s->mem_index); + gen_op_st_T0_A0(s, OT_LONG); } break; case 5: /* lfence */