From patchwork Thu Nov 21 02:38:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 292937 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 399C82C014D for ; Thu, 21 Nov 2013 13:51:22 +1100 (EST) Received: from localhost ([::1]:58225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjKMR-00062F-5l for incoming@patchwork.ozlabs.org; Wed, 20 Nov 2013 21:51:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54986) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjKDE-0007xi-07 for qemu-devel@nongnu.org; Wed, 20 Nov 2013 21:41:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VjKD9-0004Ms-LT for qemu-devel@nongnu.org; Wed, 20 Nov 2013 21:41:47 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42553) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjKD9-0004Mn-AY for qemu-devel@nongnu.org; Wed, 20 Nov 2013 21:41:43 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rAL2fYNj002858 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 20 Nov 2013 21:41:35 -0500 Received: from dell-pet610-01.lab.eng.brq.redhat.com (dell-pet610-01.lab.eng.brq.redhat.com [10.34.42.20]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id rAL2djGF031356; Wed, 20 Nov 2013 21:41:30 -0500 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Thu, 21 Nov 2013 03:38:44 +0100 Message-Id: <1385001528-12003-24-git-send-email-imammedo@redhat.com> In-Reply-To: <1385001528-12003-1-git-send-email-imammedo@redhat.com> References: <1385001528-12003-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: peter.maydell@linaro.org, stefanha@redhat.com, mst@redhat.com, chegu_vinod@hp.com, stefanb@linux.vnet.ibm.com, mjt@tls.msk.ru, mdroth@linux.vnet.ibm.com, armbru@redhat.com, vasilis.liaskovitis@profitbricks.com, quintela@redhat.com, kraxel@redhat.com, aliguori@amazon.com, hutao@cn.fujitsu.com, pbonzini@redhat.com, marcel.a@redhat.com, lcapitulino@redhat.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH 23/27] pc: ACPI BIOS: implement memory hotplug interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org - provides static SSDT object for memory hotplug - SSDT template for memory devices and runtime generator of them in SSDT table. Signed-off-by: Vasilis Liaskovitis Signed-off-by: Igor Mammedov --- mst/pci tree specific change: acpi-build: s/build_append_notify/build_append_notify_method/ introduced by "acpi-build: enable hotplug for PCI bridges" should be moved to separate patch since it's generic internal API rename. --- hw/i386/Makefile.objs | 3 +- hw/i386/acpi-build.c | 36 ++++++++++ hw/i386/ssdt-mem.dsl | 75 ++++++++++++++++++++ hw/i386/ssdt-misc.dsl | 179 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 292 insertions(+), 1 deletions(-) create mode 100644 hw/i386/ssdt-mem.dsl diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs index 185aacb..f9262a1 100644 --- a/hw/i386/Makefile.objs +++ b/hw/i386/Makefile.objs @@ -9,7 +9,8 @@ obj-y += acpi-build.o obj-y += bios-linker-loader.o hw/i386/acpi-build.o: hw/i386/acpi-build.c hw/i386/acpi-dsdt.hex \ hw/i386/ssdt-proc.hex hw/i386/ssdt-pcihp.hex hw/i386/ssdt-misc.hex \ - hw/i386/acpi-dsdt.hex hw/i386/q35-acpi-dsdt.hex + hw/i386/acpi-dsdt.hex hw/i386/q35-acpi-dsdt.hex \ + hw/i386/q35-acpi-dsdt.hex hw/i386/ssdt-mem.hex iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \ ; then echo "$(2)"; else echo "$(3)"; fi ;) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 93ffb17..d41fd81 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -36,6 +36,7 @@ #include "hw/nvram/fw_cfg.h" #include "bios-linker-loader.h" #include "hw/loader.h" +#include "qemu/config-file.h" /* Supported chipsets: */ #include "hw/acpi/piix4.h" @@ -69,6 +70,7 @@ typedef struct AcpiPmInfo { uint32_t gpe0_blk; uint32_t gpe0_blk_len; uint32_t io_base; + uint16_t mem_hotplug_io_base; } AcpiPmInfo; typedef struct AcpiMiscInfo { @@ -176,6 +178,8 @@ static void acpi_get_pm_info(AcpiPmInfo *pm) NULL); pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN, NULL); + pm->mem_hotplug_io_base = + object_property_get_int(obj, ACPI_MEMORY_HOTPLUG_IO_BASE_PROP, NULL); } static void acpi_get_misc_info(AcpiMiscInfo *info) @@ -632,6 +636,14 @@ static inline char acpi_get_hex(uint32_t val) #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start) #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start) +#include "hw/i386/ssdt-mem.hex" + +/* 0x5B 0x82 DeviceOp PkgLength NameString DimmID */ +#define ACPI_MEM_OFFSET_HEX (*ssdt_mem_name - *ssdt_mem_start + 2) +#define ACPI_MEM_OFFSET_ID (*ssdt_mem_id - *ssdt_mem_start + 7) +#define ACPI_MEM_SIZEOF (*ssdt_mem_end - *ssdt_mem_start) +#define ACPI_MEM_AML (ssdm_mem_aml + *ssdt_mem_start) + #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */ #define ACPI_SSDT_HEADER_LENGTH 36 @@ -897,6 +909,8 @@ build_ssdt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, PcPciInfo *pci, PcGuestInfo *guest_info) { + QemuOpts *opts = qemu_opts_find(qemu_find_opts("memory-opts"), NULL); + uint32_t nr_mem = qemu_opt_get_number(opts, "slots", 0); int acpi_cpus = MIN(0xff, guest_info->apic_id_limit); int ssdt_start = table_data->len; uint8_t *ssdt_ptr; @@ -920,6 +934,10 @@ build_ssdt(GArray *table_data, GArray *linker, *(uint16_t *)(ssdt_ptr + *ssdt_isa_pest) = cpu_to_le16(misc->pvpanic_port); + *(uint16_t *)(ssdt_ptr + *ssdt_mctrl_port) = + cpu_to_le16(pm->mem_hotplug_io_base); + *(int32_t *)(ssdt_ptr + *ssdt_mctrl_nr_slots) = cpu_to_le32(nr_mem); + { GArray *sb_scope = build_alloc_array(); uint8_t op = 0x10; /* ScopeOp */ @@ -961,6 +979,24 @@ build_ssdt(GArray *table_data, GArray *linker, build_free_array(package); } + if (nr_mem) { + /* build memory devices */ + for (i = 0; i < nr_mem; i++) { + char id[3]; + uint8_t *mem = acpi_data_push(sb_scope, ACPI_MEM_SIZEOF); + + snprintf(id, sizeof(id), "%02x", i); + memcpy(mem, ACPI_MEM_AML, ACPI_MEM_SIZEOF); + memcpy(mem + ACPI_MEM_OFFSET_HEX, id, 2); + memcpy(mem + ACPI_MEM_OFFSET_ID, id, 2); + } + + /* build Method(MTFY, 2) { + * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... + */ + build_append_notify_method(sb_scope, "MTFY", "MP%0.02X", nr_mem); + } + { AcpiBuildPciBusHotplugState hotplug_state; PCIBus *bus = find_i440fx(); /* TODO: Q35 support */ diff --git a/hw/i386/ssdt-mem.dsl b/hw/i386/ssdt-mem.dsl new file mode 100644 index 0000000..7f68750 --- /dev/null +++ b/hw/i386/ssdt-mem.dsl @@ -0,0 +1,75 @@ +/* + * Memory hotplug ACPI DSDT static objects definitions + * + * Copyright ProfitBricks GmbH 2012 + * Copyright (C) 2013 Red Hat Inc + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + */ + +/* This file is the basis for the ssdt_mem[] variable in src/acpi.c. + * It defines the contents of the memory device object. At + * runtime, a dynamically generated SSDT will contain one copy of this + * AML snippet for every possible memory device in the system. The + * objects will be placed in the \_SB_ namespace. + * + * In addition to the aml code generated from this file, the + * src/acpi.c file creates a MTFY method with an entry for each memdevice: + * Method(MTFY, 2) { + * If (LEqual(Arg0, 0x00)) { Notify(MP00, Arg1) } + * If (LEqual(Arg0, 0x01)) { Notify(MP01, Arg1) } + * ... + * } + */ +ACPI_EXTRACT_ALL_CODE ssdm_mem_aml + +DefinitionBlock ("ssdt-mem.aml", "SSDT", 0x02, "BXPC", "CSSDT", 0x1) +{ + + External(\_SB.MHPD.MCRS, MethodObj) + External(\_SB.MHPD.MRST, MethodObj) + External(\_SB.MHPD.MOST, MethodObj) + External(\_SB.MHPD.MPXM, MethodObj) + + Scope(\_SB) { +/* v------------------ DO NOT EDIT ------------------v */ + ACPI_EXTRACT_DEVICE_START ssdt_mem_start + ACPI_EXTRACT_DEVICE_END ssdt_mem_end + ACPI_EXTRACT_DEVICE_STRING ssdt_mem_name + Device(MPAA) { + ACPI_EXTRACT_NAME_STRING ssdt_mem_id + Name(_UID, "0xAA") +/* ^------------------ DO NOT EDIT ------------------^ + * Don't change the above without also updating the C code. + */ + Name(_HID, EISAID("PNP0C80")) + + Method(_CRS, 0) { + Return(\_SB.MHPD.MCRS(_UID)) + } + + Method(_STA, 0) { + Return(\_SB.MHPD.MRST(_UID)) + } + + Method(_PXM, 0) { + Return(\_SB.MHPD.MPXM(_UID)) + } + + Method(_OST, 3) { + \_SB.MHPD.MOST(_UID, Arg0, Arg1, Arg2) + } + } + } +} diff --git a/hw/i386/ssdt-misc.dsl b/hw/i386/ssdt-misc.dsl index a4484b8..b0c581e 100644 --- a/hw/i386/ssdt-misc.dsl +++ b/hw/i386/ssdt-misc.dsl @@ -116,4 +116,183 @@ DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1) } } } + + External(MTFY, MethodObj) + + Scope(\_SB) { + Device(MHPD) { + Name(_HID, EISAID("PNP0C08")) + + ACPI_EXTRACT_NAME_WORD_CONST ssdt_mctrl_port + Name(MHPP, 0xFFFF) + + ACPI_EXTRACT_NAME_DWORD_CONST ssdt_mctrl_nr_slots + Name(MDNR, 0x12345678) + + /* Memory hotplug IO registers */ + OperationRegion(HPMR, SystemIO, MHPP, 24) + + Method(_CRS, 0, Serialized) { + Name(CRS, ResourceTemplate() { + IO(Decode16, 0x00, 0x00, 0x01, 24, IO) + }) + + CreateWordField(CRS, IO._MIN, IOMN) + CreateWordField(CRS, IO._MAX, IOMX) + + Store(MHPP, IOMN) + Subtract(Add(MHPP, 24), 1, IOMX) + Return(CRS) + } + + Method(_STA, 0) { + If (LEqual(MDNR, Zero)) { + Return(0x0) + } + /* Leave bit 0 cleared to avoid Windows BSOD */ + Return(0xA) + } + + Field(HPMR, DWordAcc, NoLock, Preserve) { + MRBL, 32, // DIMM start addr Low word, read only + MRBH, 32, // DIMM start addr Hi word, read only + MRLL, 32, // DIMM size Low word, read only + MRLH, 32, // DIMM size Hi word, read only + MPX, 32, // DIMM node proximity, read only + } + Field(HPMR, ByteAcc, NoLock, Preserve) { + Offset(20), + MVER, 8, // Interface version + MES, 1, // 1 if DIMM enabled for _STA, read only + MINS, 1, // (read) 1 if DIMM has a insert event. (write) 1 after MTFY() + MRMV, 1, // 1 if DIMM has a remove request, read only + } + + Mutex (MLCK, 0) + Field (HPMR, DWordAcc, NoLock, Preserve) { + MSEL, 32, // DIMM selector, write only + MOEV, 32, // _OST event code, write only + MOSC, 32, // _OST status code, write only + } + + Method(MESC, 0, Serialized) { + If (LEqual(MDNR, Zero)) { + Return(Zero) + } + + Store(Zero, Local0) // Mem devs iterrator + Acquire(MLCK, 0xFFFF) + while (LLess(Local0, MDNR)) { + Store(Local0, MSEL) // select Local0 DIMM + If (LEqual(MINS, One)) { // Memory device needs check + MTFY(Local0, 1) + Store(1, MINS) + } + If (LEqual(MRMV, One)) { // Ejection request + MTFY(Local0, 3) + } + Add(Local0, One, Local0) // goto next DIMM + } + Release(MLCK) + Return(One) + } + + Method(MRST, 1) { + Store(Zero, Local0) + + Acquire(MLCK, 0xFFFF) + Store(ToInteger(Arg0), MSEL) // select DIMM + + If (LEqual(MES, One)) { + Store(0xF, Local0) + } + + Release(MLCK) + Return(Local0) + } + + Method(MCRS, 1, Serialized) { + Acquire(MLCK, 0xFFFF) + Store(ToInteger(Arg0), MSEL) // select DIMM + + Name(MR64, ResourceTemplate() { + QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x0000000000000000, // Address Space Granularity + 0x0000000000000000, // Address Range Minimum + 0xFFFFFFFFFFFFFFFE, // Address Range Maximum + 0x0000000000000000, // Address Translation Offset + 0xFFFFFFFFFFFFFFFF, // Address Length + ,, MW64, AddressRangeMemory, TypeStatic) + }) + + CreateDWordField(MR64, 14, MINL) + CreateDWordField(MR64, 18, MINH) + CreateDWordField(MR64, 38, LENL) + CreateDWordField(MR64, 42, LENH) + CreateDWordField(MR64, 22, MAXL) + CreateDWordField(MR64, 26, MAXH) + + Store(MRBH, MINH) + Store(MRBL, MINL) + Store(MRLH, LENH) + Store(MRLL, LENL) + + // 64-bit math: MAX = MIN + LEN - 1 + Add(MINL, LENL, MAXL) + Add(MINH, LENH, MAXH) + If (Or(LLess(MAXL, MINL), LLess(MAXL, LENL))) { + Add(MAXH, 1, MAXH) + } + // Ignore (MAXL == 0 & MAXH == 0) case + If (LEqual(MAXL, Zero)) { + Subtract(MAXH, One, MAXH) + Store(0xFFFFFFFF, MAXL) + } Else { + Subtract(MAXL, One, MAXL) + } + + If (LEqual(MAXH, Zero)){ + Name(MR32, ResourceTemplate() { + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0xFFFFFFFE, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0xFFFFFFFF, // Address Length + ,, MW32, AddressRangeMemory, TypeStatic) + }) + CreateDWordField(MR32, MW32._MIN, MIN) + CreateDWordField(MR32, MW32._MAX, MAX) + CreateDWordField(MR32, MW32._LEN, LEN) + Store(MINL, MIN) + Store(MAXL, MAX) + Store(LENL, LEN) + + Release(MLCK) + Return(MR32) + } + + Release(MLCK) + Return(MR64) + } + + Method(MPXM, 1) { + Acquire(MLCK, 0xFFFF) + Store(ToInteger(Arg0), MSEL) // select DIMM + Store(MPX, Local0) + Release(MLCK) + Return(Local0) + } + + Method(MOST, 4) { + Acquire(MLCK, 0xFFFF) + Store(ToInteger(Arg0), MSEL) // select DIMM + Store(Arg1, MOEV) + Store(Arg2, MOSC) + Release(MLCK) + } + } // Device() + } // Scope() }