From patchwork Tue Nov 19 06:18:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 292294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8CBBB2C0094 for ; Tue, 19 Nov 2013 17:20:39 +1100 (EST) Received: from localhost ([::1]:47345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Viefs-0003tI-Rw for incoming@patchwork.ozlabs.org; Tue, 19 Nov 2013 01:20:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vieci-00006z-Sl for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Viecd-0004lf-1l for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:20 -0500 Received: from mail-pa0-f53.google.com ([209.85.220.53]:37794) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Viecc-0004lX-Ml for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:14 -0500 Received: by mail-pa0-f53.google.com with SMTP id hz1so4685227pad.40 for ; Mon, 18 Nov 2013 22:17:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EP7BYxZY94N5+GFmQgCDjjSQuixPqMxXZVEZ6SWkdmc=; b=J2etkB698SP1pmRFTCS/TdHwGvOHJI2NV2GNBIPBcD+wwqm228s4jrD/S0wv7GjzAg WyZ/q5lbETYTyaP7K4C1bCNskyx3XTTdyfl6JzSIaN8ovTghjECQIPqas6h4BRUeYS5e fQUpoa5D8ukOsDyCZmdtAytnXLs7gbBk0rXK3RkhryTbC9+lRL1g66F88VZuqvKGUcGl 35fdUkblYGSTuXBDn1nqzSp8F46M8zTbNS0FZorfGOq/KSUzVUI6k7Kz8tggFIosFug1 BCbCyFWWe3EeFXOCkCdsERfcxiTG6q6Wx96Q++dkfsahEtAmOaBHfUF2CdQUveEKL+gm Yoww== X-Gm-Message-State: ALoCoQkdf6QeyNKd3FlI+NEvR+jiUyBaJYb6iThGnGkiSOkmat3dCRQfIpA9gcyds7eJ1EBZOG5f X-Received: by 10.66.147.9 with SMTP id tg9mr25135340pab.5.1384841833965; Mon, 18 Nov 2013 22:17:13 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id rz6sm19165159pab.22.2013.11.18.22.17.12 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 18 Nov 2013 22:17:13 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Mon, 18 Nov 2013 22:18:12 -0800 Message-Id: <1384841896-19566-7-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> References: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.53 Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Subject: [Qemu-devel] [RFC PATCH v3 06/10] arm_gic: Keep track of GICD_CPENDR and GICD_SPENDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If software writes to the ISPENDR and sets the pending state of a level-triggered interrupt, the falling edge of the hardware input must not clear the pending state. Conversely, if software writes to the ICPENDR, the pending state of a level-triggered interrupt should only be cleared if the hardware input is not asserted. This requires an extra state variable to keep track of software writes. Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 20 +++++++++++++++++--- hw/intc/arm_gic_common.c | 5 +++-- hw/intc/gic_internal.h | 3 +++ include/hw/intc/arm_gic_common.h | 1 + 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5736b95..9811161 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -119,6 +119,12 @@ static void gic_clear_pending(GICState *s, int irq, int cm, uint8_t src) GIC_CLEAR_PENDING(irq, cm); } } else { + /* If a level-triggered interrupt has been set to pending through the + * GICD_SPENDR, then a falling edge does not clear the pending state. + */ + if (GIC_TEST_SW_PENDING(irq, cm)) + return; + GIC_CLEAR_PENDING(irq, cm); } } @@ -189,8 +195,9 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) s->last_active[new_irq][cpu] = s->running_irq[cpu]; /* Clear pending flags for both level and edge triggered interrupts. Level triggered IRQs will be reasserted once they become inactive. */ - gic_clear_pending(s, new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm, - GIC_SGI_SRC(new_irq, cpu)); + cm = GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm; + GIC_CLEAR_SW_PENDING(new_irq, cm); + gic_clear_pending(s, new_irq, cm, GIC_SGI_SRC(new_irq, cpu)); gic_set_running_irq(s, cpu, new_irq); DPRINTF("ACK %d\n", new_irq); return new_irq; @@ -454,16 +461,23 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, for (i = 0; i < 8; i++, irq++) { if (irq >= GIC_NR_SGIS && value & (1 << i)) { GIC_SET_PENDING(irq, GIC_TARGET(irq)); + if (!GIC_TEST_EDGE_TRIGGER(irq)) { + GIC_SET_SW_PENDING(irq, GIC_TARGET(irq)); + } } } } else if (offset < 0x300) { + int cm = (1 << cpu); /* Interrupt Clear Pending. */ irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; for (i = 0; i < 8; i++, irq++) { if (irq >= GIC_NR_SGIS && value & (1 << i)) { - gic_clear_pending(s, irq, 1 << cpu, 0); + GIC_CLEAR_SW_PENDING(irq, cm); + if (GIC_TEST_EDGE_TRIGGER(irq) || !GIC_TEST_LEVEL(irq, cm)) { + GIC_CLEAR_PENDING(irq, cm); + } } } } else if (offset < 0x400) { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 41ddc9b..65e3dc8 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -43,11 +43,12 @@ static int gic_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_gic_irq_state = { .name = "arm_gic_irq_state", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT8(enabled, gic_irq_state), VMSTATE_UINT8(pending, gic_irq_state), + VMSTATE_UINT8(sw_pending, gic_irq_state), VMSTATE_UINT8(active, gic_irq_state), VMSTATE_UINT8(level, gic_irq_state), VMSTATE_BOOL(model, gic_irq_state), diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 5471749..b04cb50 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -35,6 +35,9 @@ #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm) #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm) #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) +#define GIC_SET_SW_PENDING(irq, cm) (s->irq_state[irq].sw_pending |= (cm)) +#define GIC_CLEAR_SW_PENDING(irq, cm) (s->irq_state[irq].sw_pending &= ~(cm)) +#define GIC_TEST_SW_PENDING(irq, cm) ((s->irq_state[irq].sw_pending & (cm)) != 0) #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm) #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm) #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 120d6b2..2d6c23f 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -35,6 +35,7 @@ typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ uint8_t enabled; uint8_t pending; + uint8_t sw_pending; /* keep track of GICD_ISPENDR and GICD_ICPENDR writes */ uint8_t active; uint8_t level; bool model; /* 0 = N:N, 1 = 1:N */