From patchwork Tue Nov 19 06:18:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 292292 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6F2DB2C0096 for ; Tue, 19 Nov 2013 17:19:19 +1100 (EST) Received: from localhost ([::1]:47322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vieea-00022J-RW for incoming@patchwork.ozlabs.org; Tue, 19 Nov 2013 01:19:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Viech-0008Vi-3z for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Viecb-0004lN-66 for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:18 -0500 Received: from mail-pb0-f51.google.com ([209.85.160.51]:55603) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vieca-0004lH-Ta for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:13 -0500 Received: by mail-pb0-f51.google.com with SMTP id up15so3127795pbc.38 for ; Mon, 18 Nov 2013 22:17:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dACFcLKX6uo2IKIBP74s+yGxSxN9pelgnYaNdkZKXlE=; b=N/KsnR2kbu27iLsdBUxLL7MnMyvnl3hTCUiBGeRRm/pAeA/WDLY+KSmRvMHMiD8j5g +2J7gNzQbtcqvEmZinELc+UeyZtvRbQiwgt46m4BR1gshbJSHQ1+mzFdv8sIxc4Ye9w6 Z3TCj133CICCNMa2VFeoAeUbuBPiyrktLrxJSSeW44e3RYrE8hVd5g2iozVUPL9F3xWC swsCXeqZo8J2mgzwH4v/SQ2ojyJSuB3Vvsode4EaIMTsvrWUo/7/eFT+HdZRDlmQApt6 kPULfmKKm3HS7LUn50OHHO6erNnLxh/KFsMyQUcRb7x56ulEVUJlQnMcwBepf/Ohcw7u AOzg== X-Gm-Message-State: ALoCoQlfLixEncUyf7IgkOZGl8XuPCz64+oYZO8xB+POooOZUIqbGe9XZundr20oMbpAKUtAX49T X-Received: by 10.68.203.164 with SMTP id kr4mr24965179pbc.48.1384841832229; Mon, 18 Nov 2013 22:17:12 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id rz6sm19165159pab.22.2013.11.18.22.17.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 18 Nov 2013 22:17:11 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Mon, 18 Nov 2013 22:18:11 -0800 Message-Id: <1384841896-19566-6-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> References: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.160.51 Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Subject: [Qemu-devel] [RFC PATCH v3 05/10] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Signed-off-by: Christoffer Dall Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 12 ++++++------ hw/intc/arm_gic_common.c | 2 +- hw/intc/gic_internal.h | 6 +++--- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 73acf62..5736b95 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -157,7 +157,7 @@ static void gic_set_irq(void *opaque, int irq, int level) DPRINTF("Set %d pending mask %x\n", irq, target); GIC_SET_PENDING(irq, target); } else { - if (!GIC_TEST_TRIGGER(irq)) { + if (!GIC_TEST_EDGE_TRIGGER(irq)) { gic_clear_pending(s, irq, target, 0); } GIC_CLEAR_LEVEL(irq, cm); @@ -225,7 +225,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq) return; /* No active IRQ. */ /* Mark level triggered interrupts as pending if they are still raised. */ - if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) + if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { DPRINTF("Set %d pending mask %x\n", irq, cm); GIC_SET_PENDING(irq, cm); @@ -348,7 +348,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) for (i = 0; i < 4; i++) { if (GIC_TEST_MODEL(irq + i)) res |= (1 << (i * 2)); - if (GIC_TEST_TRIGGER(irq + i)) + if (GIC_TEST_EDGE_TRIGGER(irq + i)) res |= (2 << (i * 2)); } } else if (offset < 0xfe0) { @@ -423,7 +423,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, /* If a raised level triggered IRQ enabled then mark is as pending. */ if (GIC_TEST_LEVEL(irq + i, mask) - && !GIC_TEST_TRIGGER(irq + i)) { + && !GIC_TEST_EDGE_TRIGGER(irq + i)) { DPRINTF("Set %d pending mask %x\n", irq + i, mask); GIC_SET_PENDING(irq + i, mask); } @@ -505,9 +505,9 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, GIC_CLEAR_MODEL(irq + i); } if (value & (2 << (i * 2))) { - GIC_SET_TRIGGER(irq + i); + GIC_SET_EDGE_TRIGGER(irq + i); } else { - GIC_CLEAR_TRIGGER(irq + i); + GIC_CLEAR_EDGE_TRIGGER(irq + i); } } } else { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 6fbdafc..41ddc9b 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -129,7 +129,7 @@ static void arm_gic_common_reset(DeviceState *dev) } for (i = 0; i < 16; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); - GIC_SET_TRIGGER(i); + GIC_SET_EDGE_TRIGGER(i); } if (s->num_cpu == 1) { /* For uniprocessor GICs all interrupts always target the sole CPU */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 3d36653..5471749 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -44,9 +44,9 @@ #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) -#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true -#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false -#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger +#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].trigger = true +#define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].trigger = false +#define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].trigger) #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL])