From patchwork Mon Nov 18 21:49:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 292219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1A1352C00B3 for ; Tue, 19 Nov 2013 09:09:42 +1100 (EST) Received: from localhost ([::1]:46050 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViWmz-0006tB-6Z for incoming@patchwork.ozlabs.org; Mon, 18 Nov 2013 16:55:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55132) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViWit-0001K8-5J for qemu-devel@nongnu.org; Mon, 18 Nov 2013 16:51:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ViWin-0004IB-SA for qemu-devel@nongnu.org; Mon, 18 Nov 2013 16:51:11 -0500 Received: from mail-pb0-x229.google.com ([2607:f8b0:400e:c01::229]:49998) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViWin-0004Ho-Gx for qemu-devel@nongnu.org; Mon, 18 Nov 2013 16:51:05 -0500 Received: by mail-pb0-f41.google.com with SMTP id jt11so7363884pbb.0 for ; Mon, 18 Nov 2013 13:51:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=xGC3kFm7PZk+WDTceBryje6hLWXYeywM0+HnrQMz90o=; b=nrQ1CoWS+Th/y/bf5uoEH7IdlevPx1XFyfHHaTUseTS76VJ85qYS3XGKChN1JEO6Hv UF9Eilxi7kYb4eH58YPTzFK8t8rA91gcY/gQOK2QoXSEwufHJ9ejvQKykF9EUu8lKJ3a fSXXE0ZpVqabJ3Qbn8GrE3c4vElXkzuq8TSXK/vjUtutBSvxogjhuXZXFBtordZwuYq5 RzNON6G6NKGhZPQI8dRvsDb+VmoPExsZM0YpXLErJLL793rGz7ygL1tB2VQOLuZaXI5K 4NuanbYrzWxmLuDcJ/As2tkQjF1OSzN4pP+EJkgoXqKAZIRNZ6wdjzLRVZnAHwWxqvPF Rh3g== X-Received: by 10.68.219.167 with SMTP id pp7mr5412071pbc.125.1384811464553; Mon, 18 Nov 2013 13:51:04 -0800 (PST) Received: from pebble.com (60-240-168-241.static.tpgi.com.au. [60.240.168.241]) by mx.google.com with ESMTPSA id gh3sm25680728pbb.2.2013.11.18.13.51.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Nov 2013 13:51:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Nov 2013 07:49:51 +1000 Message-Id: <1384811395-7097-10-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1384811395-7097-1-git-send-email-rth@twiddle.net> References: <1384811395-7097-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c01::229 Cc: aliguori@amazon.com Subject: [Qemu-devel] [PULL for-1.7 09/13] tcg-ia64: Use A3 form of logical operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We can and/or/xor/andcm small constants, saving one cycle. Acked-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ia64/tcg-target.c | 64 +++++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c index 54232eb..322955b 100644 --- a/tcg/ia64/tcg-target.c +++ b/tcg/ia64/tcg-target.c @@ -263,6 +263,7 @@ enum { OPC_MOV_I_I26 = 0x00150000000ull, OPC_MOVL_X2 = 0x0c000000000ull, OPC_OR_A1 = 0x10070000000ull, + OPC_OR_A3 = 0x10170000000ull, OPC_SETF_EXP_M18 = 0x0c748000000ull, OPC_SETF_SIG_M18 = 0x0c708000000ull, OPC_SHL_I7 = 0x0f240000000ull, @@ -281,6 +282,7 @@ enum { OPC_UNPACK4_L_I2 = 0x0f860000000ull, OPC_XMA_L_F2 = 0x1d000000000ull, OPC_XOR_A1 = 0x10078000000ull, + OPC_XOR_A3 = 0x10178000000ull, OPC_ZXT1_I29 = 0x00080000000ull, OPC_ZXT2_I29 = 0x00088000000ull, OPC_ZXT4_I29 = 0x00090000000ull, @@ -1044,27 +1046,34 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, } } -static void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGReg ret, TCGArg arg1, - int const_arg1, TCGArg arg2, int const_arg2) +static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, uint64_t opc_a3, + TCGReg ret, TCGArg arg1, int const_arg1, + TCGArg arg2, int const_arg2) { - uint64_t opc1 = 0, opc2 = 0; - - if (const_arg1 && arg1 != 0) { - opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, - TCG_REG_R2, arg1, TCG_REG_R0); - arg1 = TCG_REG_R2; - } + uint64_t opc1 = 0, opc2 = 0, opc3 = 0; if (const_arg2 && arg2 != 0) { opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3, arg2, TCG_REG_R0); arg2 = TCG_REG_R3; } + if (const_arg1 && arg1 != 0) { + if (opc_a3 && arg1 == (int8_t)arg1) { + opc3 = tcg_opc_a3(TCG_REG_P0, opc_a3, ret, arg1, arg2); + } else { + opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, + TCG_REG_R2, arg1, TCG_REG_R0); + arg1 = TCG_REG_R2; + } + } + if (opc3 == 0) { + opc3 = tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2); + } tcg_out_bundle(s, (opc1 || opc2 ? mII : miI), opc1 ? opc1 : INSN_NOP_M, opc2 ? opc2 : INSN_NOP_I, - tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2)); + opc3); } static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1, @@ -1076,29 +1085,21 @@ static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1, INSN_NOP_M, tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, arg2, arg1)); } else { - tcg_out_alu(s, OPC_ADD_A1, ret, arg1, 0, arg2, const_arg2); + tcg_out_alu(s, OPC_ADD_A1, 0, ret, arg1, 0, arg2, const_arg2); } } static inline void tcg_out_sub(TCGContext *s, TCGReg ret, TCGArg arg1, int const_arg1, TCGArg arg2, int const_arg2) { - if (const_arg1 && arg1 == (int8_t)arg1) { - if (const_arg2) { - tcg_out_movi(s, TCG_TYPE_I64, ret, arg1 - arg2); - return; - } - tcg_out_bundle(s, mmI, - INSN_NOP_M, - INSN_NOP_M, - tcg_opc_a3(TCG_REG_P0, OPC_SUB_A3, ret, arg1, arg2)); - } else if (const_arg2 && -arg2 == sextract64(-arg2, 0, 14)) { + if (!const_arg1 && const_arg2 && -arg2 == sextract64(-arg2, 0, 14)) { tcg_out_bundle(s, mmI, INSN_NOP_M, INSN_NOP_M, tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, -arg2, arg1)); } else { - tcg_out_alu(s, OPC_SUB_A1, ret, arg1, const_arg1, arg2, const_arg2); + tcg_out_alu(s, OPC_SUB_A1, OPC_SUB_A3, ret, + arg1, const_arg1, arg2, const_arg2); } } @@ -2112,13 +2113,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_and_i32: case INDEX_op_and_i64: - tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1], - args[2], const_args[2]); + /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */ + tcg_out_alu(s, OPC_AND_A1, OPC_AND_A3, args[0], + args[2], const_args[2], args[1], const_args[1]); break; case INDEX_op_andc_i32: case INDEX_op_andc_i64: - tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1], - args[2], const_args[2]); + tcg_out_alu(s, OPC_ANDCM_A1, OPC_ANDCM_A3, args[0], + args[1], const_args[1], args[2], const_args[2]); break; case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: @@ -2137,8 +2139,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_or_i32: case INDEX_op_or_i64: - tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1], - args[2], const_args[2]); + /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */ + tcg_out_alu(s, OPC_OR_A1, OPC_OR_A3, args[0], + args[2], const_args[2], args[1], const_args[1]); break; case INDEX_op_orc_i32: case INDEX_op_orc_i64: @@ -2147,8 +2150,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_xor_i32: case INDEX_op_xor_i64: - tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1], - args[2], const_args[2]); + /* TCG expects arg2 constant; A3 expects arg1 constant. Swap. */ + tcg_out_alu(s, OPC_XOR_A1, OPC_XOR_A3, args[0], + args[2], const_args[2], args[1], const_args[1]); break; case INDEX_op_mul_i32: