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[138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.07.14 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:04:51 +1000 Message-Id: <1383786324-18415-29-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::22d Subject: [Qemu-devel] [PATCH for-1.8 28/61] target-i386: Remove gen_op_andl_T0_ffff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Replace it with tcg_gen_ext16u_tl. In four places we can combine that with a previous move into cpu_T[0], and in one place we can infer that the zero-extension has already happened via the previous load. Signed-off-by: Richard Henderson --- target-i386/translate.c | 43 ++++++++++++++++++------------------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 2fa222b..b8a8954 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,11 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_andl_T0_ffff(void) -{ - tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); -} - static inline void gen_op_andl_T0_im(uint32_t val) { tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val); @@ -5000,8 +4995,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 2: /* call Ev */ /* XXX: optimize if memory (no 'and' is necessary) */ - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } next_eip = s->pc - s->cs_base; tcg_gen_movi_tl(cpu_T[1], next_eip); gen_push_T1(s); @@ -5029,8 +5025,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_eob(s); break; case 4: /* jmp Ev */ - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } gen_op_jmp_T0(); gen_eob(s); break; @@ -6415,8 +6412,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -6434,8 +6430,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes) | 4); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -6497,8 +6492,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); if (use_icount) @@ -6517,8 +6511,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = MO_8; else ot = dflag ? MO_32 : MO_16; - gen_op_mov_TN_reg(MO_16, 0, R_EDX); - gen_op_andl_T0_ffff(); + tcg_gen_ext16u_tl(cpu_T[0], cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); gen_op_mov_TN_reg(ot, 1, R_EAX); @@ -6543,16 +6536,18 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (CODE64(s) && s->dflag) s->dflag = 2; gen_stack_update(s, val + (2 << s->dflag)); - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } gen_op_jmp_T0(); gen_eob(s); break; case 0xc3: /* ret */ gen_pop_T0(s); gen_pop_update(s); - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + if (s->dflag == 0) { + tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]); + } gen_op_jmp_T0(); gen_eob(s); break; @@ -6568,15 +6563,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_stack_A0(s); /* pop offset */ - gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0); - if (s->dflag == 0) - gen_op_andl_T0_ffff(); + gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); /* NOTE: keeping EIP updated is not a problem in case of exception */ gen_op_jmp_T0(); /* pop selector */ gen_op_addl_A0_im(2 << s->dflag); - gen_op_ld_v(s, 1 + s->dflag, cpu_T[0], cpu_A0); + gen_op_ld_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); gen_op_movl_seg_T0_vm(R_CS); /* add stack offset */ gen_stack_update(s, val + (4 << s->dflag));