From patchwork Tue Oct 29 19:04:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Macke X-Patchwork-Id: 287034 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 44C472C0367 for ; Wed, 30 Oct 2013 06:10:19 +1100 (EST) Received: from localhost ([::1]:48932 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEgD-0001i2-9h for incoming@patchwork.ozlabs.org; Tue, 29 Oct 2013 15:10:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEbh-0003uS-DG for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:05:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VbEba-0005RP-Dy for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:05:37 -0400 Received: from www11.your-server.de ([213.133.104.11]:60011) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbEba-0005RF-4h for qemu-devel@nongnu.org; Tue, 29 Oct 2013 15:05:30 -0400 Received: from [142.103.140.43] (helo=openrisc-VirtualBox.phas.ubc.ca) by www11.your-server.de with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.74) (envelope-from ) id 1VbEbY-00075y-Qr; Tue, 29 Oct 2013 20:05:29 +0100 From: Sebastian Macke To: qemu-devel@nongnu.org, proljc@gmail.com Date: Tue, 29 Oct 2013 20:04:50 +0100 Message-Id: <1383073495-5332-9-git-send-email-sebastian@macke.de> X-Mailer: git-send-email 1.8.4.1 In-Reply-To: <1383073495-5332-1-git-send-email-sebastian@macke.de> References: <1383073495-5332-1-git-send-email-sebastian@macke.de> X-Authenticated-Sender: sebastian@macke.de X-Virus-Scanned: Clear (ClamAV 0.97.8/18033/Tue Oct 29 17:37:37 2013) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 213.133.104.11 Cc: Sebastian Macke , openrisc@lists.openrisc.net, openrisc@lists.opencores.org Subject: [Qemu-devel] [PATCH 08/13] target-openrisc: Test for Overflow exception statically X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instead of testing the overflow exception dynamically every time The flag will be reckognized by the tcg as changed code and will recompile the code with the correct checks. Signed-off-by: Sebastian Macke --- target-openrisc/cpu.h | 3 +- target-openrisc/translate.c | 78 ++++++++++++++++++++++++++------------------- 2 files changed, 48 insertions(+), 33 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index bac61e5..94bbb17 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -412,7 +412,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, *pc = env->pc; *cs_base = 0; /* D_FLAG -- branch instruction exception */ - *flags = (env->flags & D_FLAG) | (env->sr & (SR_SM | SR_DME | SR_IME)); + *flags = (env->flags & D_FLAG) | + (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } static inline int cpu_mmu_index(CPUOpenRISCState *env) diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 9fd1126..b1f73c4 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -271,7 +271,6 @@ static void dec_calc(DisasContext *dc, uint32_t insn) TCGv_i64 tb = tcg_temp_new_i64(); TCGv_i64 td = tcg_temp_local_new_i64(); TCGv_i32 res = tcg_temp_local_new_i32(); - TCGv_i32 sr_ove = tcg_temp_local_new_i32(); tcg_gen_extu_i32_i64(ta, cpu_R[ra]); tcg_gen_extu_i32_i64(tb, cpu_R[rb]); tcg_gen_add_i64(td, ta, tb); @@ -282,16 +281,19 @@ static void dec_calc(DisasContext *dc, uint32_t insn) tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); - gen_exception(dc, EXCP_RANGE); + if (dc->tb_flags & SR_OVE) { + TCGv_i32 sr_ove = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); + gen_exception(dc, EXCP_RANGE); + tcg_temp_free_i32(sr_ove); + } gen_set_label(lab); tcg_gen_mov_i32(cpu_R[rd], res); tcg_temp_free_i64(ta); tcg_temp_free_i64(tb); tcg_temp_free_i64(td); tcg_temp_free_i32(res); - tcg_temp_free_i32(sr_ove); } break; default: @@ -312,7 +314,6 @@ static void dec_calc(DisasContext *dc, uint32_t insn) TCGv_i64 td = tcg_temp_local_new_i64(); TCGv_i32 res = tcg_temp_local_new_i32(); TCGv_i32 sr_cy = tcg_temp_local_new_i32(); - TCGv_i32 sr_ove = tcg_temp_local_new_i32(); tcg_gen_extu_i32_i64(ta, cpu_R[ra]); tcg_gen_extu_i32_i64(tb, cpu_R[rb]); tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY); @@ -327,9 +328,13 @@ static void dec_calc(DisasContext *dc, uint32_t insn) tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); - gen_exception(dc, EXCP_RANGE); + if (dc->tb_flags & SR_OVE) { + TCGv_i32 sr_ove = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); + gen_exception(dc, EXCP_RANGE); + tcg_temp_free_i32(sr_ove); + } gen_set_label(lab); tcg_gen_mov_i32(cpu_R[rd], res); tcg_temp_free_i64(ta); @@ -338,7 +343,6 @@ static void dec_calc(DisasContext *dc, uint32_t insn) tcg_temp_free_i64(td); tcg_temp_free_i32(res); tcg_temp_free_i32(sr_cy); - tcg_temp_free_i32(sr_ove); } break; default: @@ -357,7 +361,6 @@ static void dec_calc(DisasContext *dc, uint32_t insn) TCGv_i64 tb = tcg_temp_new_i64(); TCGv_i64 td = tcg_temp_local_new_i64(); TCGv_i32 res = tcg_temp_local_new_i32(); - TCGv_i32 sr_ove = tcg_temp_local_new_i32(); tcg_gen_extu_i32_i64(ta, cpu_R[ra]); tcg_gen_extu_i32_i64(tb, cpu_R[rb]); @@ -369,16 +372,19 @@ static void dec_calc(DisasContext *dc, uint32_t insn) tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); - gen_exception(dc, EXCP_RANGE); + if (dc->tb_flags & SR_OVE) { + TCGv_i32 sr_ove = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); + gen_exception(dc, EXCP_RANGE); + tcg_temp_free_i32(sr_ove); + } gen_set_label(lab); tcg_gen_mov_i32(cpu_R[rd], res); tcg_temp_free_i64(ta); tcg_temp_free_i64(tb); tcg_temp_free_i64(td); tcg_temp_free_i32(res); - tcg_temp_free_i32(sr_ove); } break; default: @@ -451,10 +457,12 @@ static void dec_calc(DisasContext *dc, uint32_t insn) TCGv_i32 sr_ove = tcg_temp_local_new_i32(); if (rb == 0) { tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0); - gen_exception(dc, EXCP_RANGE); - gen_set_label(lab0); + if (dc->tb_flags & SR_OVE) { + tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0); + gen_exception(dc, EXCP_RANGE); + gen_set_label(lab0); + } } else { tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb], 0x00000000, lab1); @@ -464,9 +472,11 @@ static void dec_calc(DisasContext *dc, uint32_t insn) 0xffffffff, lab2); gen_set_label(lab1); tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3); - gen_exception(dc, EXCP_RANGE); + if (dc->tb_flags & SR_OVE) { + tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3); + gen_exception(dc, EXCP_RANGE); + } gen_set_label(lab2); tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); gen_set_label(lab3); @@ -950,7 +960,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) TCGv_i64 ta = tcg_temp_new_i64(); TCGv_i64 td = tcg_temp_local_new_i64(); TCGv_i32 res = tcg_temp_local_new_i32(); - TCGv_i32 sr_ove = tcg_temp_local_new_i32(); tcg_gen_extu_i32_i64(ta, cpu_R[ra]); tcg_gen_addi_i64(td, ta, sign_extend(I16, 16)); tcg_gen_trunc_i64_i32(res, td); @@ -960,15 +969,18 @@ static void dec_misc(DisasContext *dc, uint32_t insn) tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); - gen_exception(dc, EXCP_RANGE); + if (dc->tb_flags & SR_OVE) { + TCGv_i32 sr_ove = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); + gen_exception(dc, EXCP_RANGE); + tcg_temp_free_i32(sr_ove); + } gen_set_label(lab); tcg_gen_mov_i32(cpu_R[rd], res); tcg_temp_free_i64(ta); tcg_temp_free_i64(td); tcg_temp_free_i32(res); - tcg_temp_free_i32(sr_ove); } } break; @@ -982,7 +994,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) TCGv_i64 tcy = tcg_temp_local_new_i64(); TCGv_i32 res = tcg_temp_local_new_i32(); TCGv_i32 sr_cy = tcg_temp_local_new_i32(); - TCGv_i32 sr_ove = tcg_temp_local_new_i32(); tcg_gen_extu_i32_i64(ta, cpu_R[ra]); tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY); tcg_gen_shri_i32(sr_cy, sr_cy, 10); @@ -996,9 +1007,13 @@ static void dec_misc(DisasContext *dc, uint32_t insn) tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); - tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); - tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); - gen_exception(dc, EXCP_RANGE); + if (dc->tb_flags & SR_OVE) { + TCGv_i32 sr_ove = tcg_temp_local_new_i32(); + tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); + tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); + gen_exception(dc, EXCP_RANGE); + tcg_temp_free_i32(sr_ove); + } gen_set_label(lab); tcg_gen_mov_i32(cpu_R[rd], res); tcg_temp_free_i64(ta); @@ -1006,7 +1021,6 @@ static void dec_misc(DisasContext *dc, uint32_t insn) tcg_temp_free_i64(tcy); tcg_temp_free_i32(res); tcg_temp_free_i32(sr_cy); - tcg_temp_free_i32(sr_ove); } break;