From patchwork Fri Sep 27 10:10:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mian M. Hamayun" X-Patchwork-Id: 278529 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 484362C0354 for ; Fri, 27 Sep 2013 20:13:42 +1000 (EST) Received: from localhost ([::1]:35175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPV2i-0000eL-3v for incoming@patchwork.ozlabs.org; Fri, 27 Sep 2013 06:13:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPV0d-0006qM-7L for qemu-devel@nongnu.org; Fri, 27 Sep 2013 06:10:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VPV0X-0004tI-71 for qemu-devel@nongnu.org; Fri, 27 Sep 2013 06:10:51 -0400 Received: from mail-wg0-f48.google.com ([74.125.82.48]:49555) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPV0X-0004tD-0a for qemu-devel@nongnu.org; Fri, 27 Sep 2013 06:10:45 -0400 Received: by mail-wg0-f48.google.com with SMTP id n12so2412000wgh.3 for ; Fri, 27 Sep 2013 03:10:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0PB2yI0usV76iMGrrxcEI9Hkqdy4FQMGAhy5ikDbYRQ=; b=gtmnUAtdXtRdiYhNrOp5VhTd7J16e2CUatj+0Ko+jtRiLTYMcukjl9BJvUCDR7BkWf iRhq+B0Juq6bCwZFW0Vbrqc7KhNkF317VjQgwD8SbSzsYTice0SVqvk40FkR+OWYal8U fQioRRV6f5/1JD7I92lpPNu89YIMvL+5FPzoL3OhnfpR08nLgKWjgtJx4VKbXAByaIs1 hUYHLk3aGvXCQejhz2zAsoPjR19m54jL+SOBMz6d49Kq/giF2In24rhO0Z6NZV83dvO2 z5Uu75zLEKniXW1e67F89omflRbKLz3DIEAL2LxPkPGo4u7VtXhNd9VL2zgMgnxfOecE mv6g== X-Gm-Message-State: ALoCoQkwdE7vWAjEgIW51mY6d0X52C8O/Wr9Rob50rhzKdVfmzIzl9kpKTTCKs11EzwP7qnqa6NZ X-Received: by 10.180.219.8 with SMTP id pk8mr1908950wic.58.1380276644390; Fri, 27 Sep 2013 03:10:44 -0700 (PDT) Received: from localhost.localdomain (133.150.193.77.rev.sfr.net. [77.193.150.133]) by mx.google.com with ESMTPSA id eg1sm8600510wib.11.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 27 Sep 2013 03:10:43 -0700 (PDT) From: "Mian M. Hamayun" To: qemu-devel@nongnu.org Date: Fri, 27 Sep 2013 12:10:11 +0200 Message-Id: <1380276614-857-9-git-send-email-m.hamayun@virtualopensystems.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1380276614-857-1-git-send-email-m.hamayun@virtualopensystems.com> References: <1380276614-857-1-git-send-email-m.hamayun@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.48 Cc: peter.maydell@linaro.org, agraf@suse.de, tech@virtualopensystems.com, kvmarm@lists.cs.columbia.edu, afaerber@suse.de Subject: [Qemu-devel] [PATCH v3 08/11] AARCH64: Enable SMP support for aarch64 processors using PSCI method X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Mian M. Hamayun" We enable SMP support for aarch64 processors using the PSCI method, by setting the appropriate CPU feature flags at initilializtion time. Secondary boot code for non-aarch64 processors is disabled in case of compilation for aarch64. Signed-off-by: Mian M. Hamayun --- hw/arm/boot.c | 4 ++++ target-arm/kvm_64.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0471eb8..ddafd3b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -157,6 +157,7 @@ static void setup_boot_env(ARMCPU *cpu) static void default_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { +#ifndef TARGET_AARCH64 int n; smpboot[smpboot_array_size - 1] = info->smp_bootreg_addr; smpboot[smpboot_array_size - 2] = info->gic_cpu_if_addr; @@ -171,15 +172,18 @@ static void default_write_secondary(ARMCPU *cpu, rom_add_blob_fixed("smpboot", smpboot, smpboot_array_size * sizeof(uint32_t), info->smp_loader_start); +#endif } static void default_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { +#ifndef TARGET_AARCH64 CPUARMState *env = &cpu->env; stl_phys_notdirty(info->smp_bootreg_addr, 0); env->regs[15] = info->smp_loader_start; +#endif } #define WRITE_WORD(p, value) do { \ diff --git a/target-arm/kvm_64.c b/target-arm/kvm_64.c index 9685727..146b7c4 100644 --- a/target-arm/kvm_64.c +++ b/target-arm/kvm_64.c @@ -27,12 +27,19 @@ static uint32_t kvm_arm_targets[KVM_ARM_NUM_TARGETS] = { KVM_ARM_TARGET_CORTEX_A57 }; +#define ARM_VCPU_FEATURE_FLAGS(cpuid, is_aarch32) \ +((!!(cpuid) << KVM_ARM_VCPU_POWER_OFF) | (is_aarch32 << KVM_ARM_VCPU_EL1_32BIT)) + int kvm_arch_init_vcpu(CPUState *cs) { struct kvm_vcpu_init init; int ret, i; + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + memset(init.features, 0, sizeof(init.features)); + init.features[0] = ARM_VCPU_FEATURE_FLAGS(cs->cpu_index, !env->aarch64); /* Find an appropriate target CPU type. * KVM does not provide means to detect the host CPU type on aarch64, * and simply refuses to initialize, if the CPU type mis-matches;