From patchwork Fri Sep 27 00:48:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 278340 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2A6FD2C033F for ; Fri, 27 Sep 2013 10:55:20 +1000 (EST) Received: from localhost ([::1]:60467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPML0-00027m-43 for incoming@patchwork.ozlabs.org; Thu, 26 Sep 2013 20:55:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPMF2-0001NR-3a for qemu-devel@nongnu.org; Thu, 26 Sep 2013 20:49:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VPMEu-0004is-N1 for qemu-devel@nongnu.org; Thu, 26 Sep 2013 20:49:08 -0400 Received: from cantor2.suse.de ([195.135.220.15]:52655 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPMEu-0004hz-GW for qemu-devel@nongnu.org; Thu, 26 Sep 2013 20:49:00 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 2ACB7A554C; Fri, 27 Sep 2013 02:48:58 +0200 (CEST) From: Alexander Graf To: qemu-devel@nongnu.org Date: Fri, 27 Sep 2013 02:48:16 +0200 Message-Id: <1380242934-20953-23-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1380242934-20953-1-git-send-email-agraf@suse.de> References: <1380242934-20953-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , Michael Matz , C Fontana , Dirk Mueller , Laurent Desnogues , Christoffer Dall , Richard Henderson Subject: [Qemu-devel] [PATCH 22/60] AArch64: Add AdvSIMD scalar three same group handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds decoding for the AdvSIMD scalar three same group with U == 0. While at it, it also adds support for the ADD / SUB operations in this group. Signed-off-by: Alexander Graf --- target-arm/translate-a64.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ad20892..9d6edf4 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1005,6 +1005,56 @@ static void handle_simdorr(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_res_2); } +/* AdvSIMD scalar three same (U=0) */ +static void handle_simd3su0(DisasContext *s, uint32_t insn) +{ + int rd = get_bits(insn, 0, 5); + int rn = get_bits(insn, 5, 5); + int opcode = get_bits(insn, 11, 5); + int rm = get_bits(insn, 16, 5); + int size = get_bits(insn, 22, 2); + bool is_sub = get_bits(insn, 29, 1); + bool is_q = get_bits(insn, 30, 1); + int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]); + int freg_offs_n = offsetof(CPUARMState, vfp.regs[rn * 2]); + int freg_offs_m = offsetof(CPUARMState, vfp.regs[rm * 2]); + TCGv_i64 tcg_op1 = tcg_temp_new_i64(); + TCGv_i64 tcg_op2 = tcg_temp_new_i64(); + TCGv_i64 tcg_res = tcg_temp_new_i64(); + int ebytes = (1 << size); + int i; + + for (i = 0; i < 16; i += ebytes) { + simd_ld(tcg_op1, freg_offs_n + i, size); + simd_ld(tcg_op2, freg_offs_m + i, size); + + switch (opcode) { + case 0x10: /* ADD / SUB */ + if (is_sub) { + tcg_gen_sub_i64(tcg_res, tcg_op1, tcg_op2); + } else { + tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2); + } + break; + default: + unallocated_encoding(s); + return; + } + + simd_st(tcg_res, freg_offs_d + i, size); + } + + if (!is_q) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + simd_st(tcg_zero, freg_offs_d + sizeof(float64), 3); + tcg_temp_free_i64(tcg_zero); + } + + tcg_temp_free_i64(tcg_op1); + tcg_temp_free_i64(tcg_op2); + tcg_temp_free_i64(tcg_res); +} + void disas_a64_insn(CPUARMState *env, DisasContext *s) { uint32_t insn; @@ -1077,6 +1127,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s) get_bits(insn, 21, 1) && get_bits(insn, 10, 1) && (get_bits(insn, 11, 5) == 0x3)) { handle_simdorr(s, insn); + } else if (!get_bits(insn, 31, 1) && get_bits(insn, 21, 1) && + get_bits(insn, 10, 1)) { + handle_simd3su0(s, insn); } else { unallocated_encoding(s); }