From patchwork Thu Sep 26 21:03:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 278274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9410C2C00BE for ; Fri, 27 Sep 2013 07:03:59 +1000 (EST) Received: from localhost ([::1]:59929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIj7-0008Co-D1 for incoming@patchwork.ozlabs.org; Thu, 26 Sep 2013 17:03:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56763) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIiR-00082N-Pi for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VPIiK-0000pZ-Jm for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:15 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:63112) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIiK-0000pB-E0 for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:08 -0400 Received: by mail-pd0-f180.google.com with SMTP id y10so1674164pdj.11 for ; Thu, 26 Sep 2013 14:03:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cRkpKisQD4SHaSAz6v6YA/FMX1vxu2tomA2wsW9hOHc=; b=Zh779RKeYz0dEbG0LsV6tUsxUP0NDzl/i+gwJd9XRN+SeX2hcM4VHZBQ2NNeplZgBD Wf4KUQFwbTjHB4IzyHV6lzK0gTp4SWQKq9Ji4VYXA3SklYbQcpm4oPA9IK/iKoiNo1bd +faVZejNMSDRYb+D1TQJA8QwIYDuax64bmUrD13L2FLpzNTo3KRWwfSDu5Pbg/a95l6I SeFMkt3AIYRhzztb4pHUMvOl4tOOZHpcLi5K844aEWtlzsDYEC2oizOH1HtlcZ342v3r UQmpzqNImQsa6HZ1FDxE8wuD0YsghNnQXU8gaXwJuNsxbjZyJl6rc6yXzsGfU9SdPGEr HnUQ== X-Gm-Message-State: ALoCoQk8JN8fKqDsxDUcT2ax8mmV6ytu8n+/4VNR5BY1tC4Xasd4ykFsrrtWotgwo0M/q9N9d/MB X-Received: by 10.68.229.2 with SMTP id sm2mr3482254pbc.68.1380229387635; Thu, 26 Sep 2013 14:03:07 -0700 (PDT) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id 7sm7385572paf.22.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 14:03:06 -0700 (PDT) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Thu, 26 Sep 2013 14:03:01 -0700 Message-Id: <1380229386-24166-2-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> References: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.180 Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Subject: [Qemu-devel] [RFC PATCH v2 1/6] hw: arm_gic: Fix gic_set_irq handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For some reason only edge-triggered or enabled level-triggered interrupts would set the pending state of a raised IRQ. This is not in compliance with the specs, which indicate that the pending state is separate from the enabled state, which only controls if a pending interrupt is actually forwarded to the CPU interface. Therefore, simply always set the pending state on a rising edge, but only clear the pending state of falling edge if the interrupt is level triggered. Changelog [v2]: - Fix bisection issue, by not using gic_clear_pending yet. Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d431b7a..c7a24d5 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -128,11 +128,12 @@ static void gic_set_irq(void *opaque, int irq, int level) if (level) { GIC_SET_LEVEL(irq, cm); - if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) { - DPRINTF("Set %d pending mask %x\n", irq, target); - GIC_SET_PENDING(irq, target); - } + DPRINTF("Set %d pending mask %x\n", irq, target); + GIC_SET_PENDING(irq, target); } else { + if (!GIC_TEST_TRIGGER(irq)) { + GIC_CLEAR_PENDING(irq, target); + } GIC_CLEAR_LEVEL(irq, cm); } gic_update(s);