From patchwork Wed Sep 25 12:57:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 277847 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 36FBC2C032F for ; Wed, 25 Sep 2013 23:10:26 +1000 (EST) Received: from localhost ([::1]:52471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOorH-0003Fk-BZ for incoming@patchwork.ozlabs.org; Wed, 25 Sep 2013 09:10:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOofz-00036S-4T for qemu-devel@nongnu.org; Wed, 25 Sep 2013 08:58:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VOoft-00009R-60 for qemu-devel@nongnu.org; Wed, 25 Sep 2013 08:58:43 -0400 Received: from mail-qc0-x230.google.com ([2607:f8b0:400d:c01::230]:63354) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOoft-00009E-1G; Wed, 25 Sep 2013 08:58:37 -0400 Received: by mail-qc0-f176.google.com with SMTP id t7so4028185qcv.35 for ; Wed, 25 Sep 2013 05:58:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=DaRhhclX7RiaPJGSBrFu9E48muQwIbeB5fEY65eGFVI=; b=d05yOD4PQo/CEy4PQllJbhm03QI/h1FwfV2tQIxws/B0NKzslvqdi5VOAaAkeJGFZX Pa4xT0j8t9oJl8vS1khiqhhVWfj1Ur5ZW3p+KeRDWkJYprL1xvWFZvRg39TSu8u8A3HU 9EmxLv/dGIKs6bfLTeRhUuuEmCxw5Udte+tSv3lNA9XjZKtRdYAO/XZ4mYtuiyn2MXtK n2WSvaqBkZiG4MQDmb7W3wW/PmWfQCUyuqnZENn6UDntKZlBlSHMjHRH17lI3FGvUXO5 Bl2n7uR2BYYM5QMBi+JhJ0/BIBPwk7CB2ngFciv8pNTMUy5bRKzF9rMbbNpPfr/WXKrk ivGQ== X-Received: by 10.49.94.172 with SMTP id dd12mr36845308qeb.4.1380113916462; Wed, 25 Sep 2013 05:58:36 -0700 (PDT) Received: from loki.morrigu.org ([70.114.130.150]) by mx.google.com with ESMTPSA id g2sm65250216qaf.12.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 25 Sep 2013 05:58:36 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Wed, 25 Sep 2013 07:57:36 -0500 Message-Id: <1380113886-16845-9-git-send-email-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1380113886-16845-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1380113886-16845-1-git-send-email-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::230 Cc: qemu-stable@nongnu.org Subject: [Qemu-devel] [PATCH 08/38] pc: fix regression for 64 bit PCI memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Michael S. Tsirkin" commit 398489018183d613306ab022653552247d93919f pc: limit 64 bit hole to 2G by default introduced a way for management to control the window allocated to the 64 bit PCI hole. This is useful, but existing management tools do not know how to set this property. As a result, e.g. specifying a large ivshmem device with size > 4G is broken by default. For example this configuration no longer works: -device ivshmem,size=4294967296,chardev=cfoo -chardev socket,path=/tmp/sock,id=cfoo,server,nowait Fix this by detecting that hole size was not specified and defaulting to the backwards-compatible value of 1 << 62. Cc: qemu-stable@nongnu.org Cc: Igor Mammedov Signed-off-by: Michael S. Tsirkin (cherry picked from commit 1466cef32dd5e7ef3c6477e96d85d92302ad02e3) Signed-off-by: Michael Roth --- hw/pci-host/piix.c | 9 ++++++--- hw/pci-host/q35.c | 8 +++++--- include/hw/i386/pc.h | 11 ++++++++++- 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index dc1718f..221d82b 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -320,6 +320,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, PCII440FXState *f; unsigned i; I440FXState *i440fx; + uint64_t pci_hole64_size; dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE); s = PCI_HOST_BRIDGE(dev); @@ -351,13 +352,15 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, pci_hole_start, pci_hole_size); memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); + pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size); + pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size, - i440fx->pci_hole64_size); + pci_hole64_size); memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64", f->pci_address_space, i440fx->pci_info.w64.begin, - i440fx->pci_hole64_size); - if (i440fx->pci_hole64_size) { + pci_hole64_size); + if (pci_hole64_size) { memory_region_add_subregion(f->system_memory, i440fx->pci_info.w64.begin, &f->pci_hole_64bit); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 12314d8..4febd24 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -320,6 +320,7 @@ static int mch_init(PCIDevice *d) { int i; MCHPCIState *mch = MCH_PCI_DEVICE(d); + uint64_t pci_hole64_size; /* setup pci memory regions */ memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", @@ -329,13 +330,14 @@ static int mch_init(PCIDevice *d) memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, &mch->pci_hole); + pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size); pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size, - mch->pci_hole64_size); + pci_hole64_size); memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", mch->pci_address_space, mch->pci_info.w64.begin, - mch->pci_hole64_size); - if (mch->pci_hole64_size) { + pci_hole64_size); + if (pci_hole64_size) { memory_region_add_subregion(mch->system_memory, mch->pci_info.w64.begin, &mch->pci_hole_64bit); diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index f79d478..475ba9e 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -106,7 +106,16 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" -#define DEFAULT_PCI_HOLE64_SIZE (1ULL << 31) +#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL) + +static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size) +{ + if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) { + return 1ULL << 62; + } else { + return pci_hole64_size; + } +} void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start, uint64_t pci_hole64_size);